ASIC, ASSP and SoC development is, and will always be, a risky and expensive business. Add to this the fact that today functional verification constitutes 50 to 70 percent of the development effort, and it becomes obvious that traditional verification methodologies are no longer by themselves sufficient to keep up with growing design complexities and shrinking design cycles.

Prototyping, because of its unparalleled verification performance and ability to act as a software development platform, is one of the fastest-growing verification methodologies. And although virtually every ASIC, ASSP and system-on-chip developed today is prototyped on an FPGA board, many still consider prototyping an ad hoc methodology rather than a mature verification solution.

That perception has some validity to it, because there is still a lot of "assembly required" to make a custom prototype board work successfully. But only prototyping offers the performance, flexibility and capabilities necessary for mastering some of the most critical verification challenges facing designers today. As a result, FPGA-based prototyping is quickly evolving, "growing up" in ways that allow it to address these challenges. FPGA-based prototyping is turning into a highly productive, easy-to-use verification methodology.

FPGA-based prototyping has been around for quite a while; but not until very recently, with the advent of a new generation of high-performance and high-density FPGAs, did prototyping become suitable for verification of virtually every ASIC, ASSP and SoC design. Today's high-density devices offer core speeds in the hundreds of megahertz and complexities of up to 2 million (ASIC) gates.

At the core of every prototyping system is the prototyping board itself. Ever since FPGA-based prototyping first emerged, design teams have usually developed their own customized boards in-house. This development effort absorbed some resources, but it was still manageable, considering the relatively limited complexity of previous FPGA generations. That has changed quickly, though. Ever-increasing design complexities and the availability of high-capacity 90- and 65-nanometer FPGAs in high-pin-count packages are driving the need for highly sophisticated boards. Today, prototype board design involves such challenges as managing 20+ board layers, tens of thousands of board-mounted components, power distribution, signal integrity and high-speed board design, among many others--and none of these issues are typically core competencies of ASIC designers. Board development has become a task that demands unique expertise. That is one of the reasons why commercial, off-the-shelf boards are quickly becoming the solution of choice.

Synplicity's Haps prototyping boards allow reuse for multiple projects.
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Prototyping systems are a critical part of the verification strategy for expensive, time-critical ASIC projects. Millions--or, in some cases, billions--of dollars in revenue may ride on getting a design done on time. Off-the-shelf boards that are closely tied to the appropriate implementation and debug tools offer the lowest-risk solution. A homegrown approach, on the other hand, might actually add risk and complexity instead of reducing it.

It's the software
The purpose of prototyping is to verify the ASIC, ASSP or SoC design and its functional correctness in the system environment. Verifying the design therefore involves more and more software, and, in fact, more prototypes are used for software development than for hardware verification. FPGA-based prototypes are the ideal verification platform because they can run software orders of magnitude faster than can any alternative methodology. RTL simulation offers convenience and great visibility into the design, but its poor performance when simulating makes it impractical for use in software development, as well as in system integration and verification. That, of course, adds a completely new set of requirements to a prototyping system: reliability, ease-of-use, ease-of-deployment and (of course) the performance needed to give software developers a platform usable for software development.

But that is not the only software aspect in play here. Implementing the design and debugging it requires not only powerful software tools, but tools that seamlessly work together and with the prototyping board itself. There is an advantage to having the prototype hardware tied into the design implementation and debug software. A closer tie between tools makes the whole process faster and less error-prone. To date, however, designers are still challenged with piecing together their own solutions: selecting different hardware and software tools from various vendors, ensuring that the tools are adequate to address particular needs and creating an ad hoc flow for tool interoperability.

Teradici Corp., a fabless semiconductor company providing PC-over-IP systems and solutions, has verified its Tera1 "hardware accelerated remote desktop over IP networks" chip set by taking advantage of FPGA-based prototyping. The goal was to set up a system, well before the availability of first silicon, to catch bugs in a "real world" environment. The setup consists of two cards--one that goes into the host PC and one in the client--realized with a multi-FPGA prototyping system.

The results were overwhelmingly positive. Teradici quickly found those elusive last few bugs, and the chip set was released to production with only a single metal revision.

What's more, all "emulated" functionality worked when chip production was released in August 2007.

Confirma is a comprehensive prototyping platform that integrates best-in-class tools into a verification solution.
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But the prototyping system helped in other ways, too. It gave the design team a one-year head start on firmware development, and when the first silicon was available, everyone was ready for final firmware integration and debugging. The prototyping system was also very useful in testing system interaction with various drivers and peripherals, such as mice, keyboards and Webcams--a feat not possible in software simulation.

What's next?
The benefits of ASIC prototyping in FPGAs are undisputed. It is a methodology for running all verification needed to achieve first-pass silicon success, and it provides the highest performance of any functional verification methodology, running more than 1 million times faster than software simulation. It also provides real-world stimulus instead of incomplete testbenches, thus acting as a platform for software development. Designers can get a head start in firmware and driver development using this methodology as a platform for system integration and verification that allows them to investigate interactions among hardware, operating systems and peripheral devices.

There are outstanding issues with using ASIC prototyping in FPGAs, however. Board design challenges can include difficulties in adhering to schedules while ensuring proper functionality. Design implementation requires designers to figure out how to map an ASIC design into FPGAs and implement multi-FPGA partitioning. The methodology also has debugging and visibility limitations. Bugs are found quickly, but then what? How are they analyzed? Thus, using FPGAs for ASIC prototyping is often thought of as a nuisance and an additional design step, though increasingly it seems the only way to ensure success.

Gone are the days when ASIC design teams could quickly build ad hoc prototypes and verify their designs. To take advantage of the full potential of prototyping, the function must be considered a powerful, mainstream verification methodology, alongside such other tools as simulation and formal verification. However, that also requires EDA vendors to rise to the challenge of providing complete, easy-to-use and affordable prototyping solutions to their customers. It is simply not sustainable to burden end users with making the various tools work together. Prototyping has to grow up.

What is needed are "best in class" hardware and software tools integrated into an easy-to-use solution. This begins with the design implementation tool, which has to condition an ASIC design, partition it and map it into a set of FPGAs while preserving ASIC functionality. User interaction and design modifications must be kept to a minimum, and ASIC-specific design constructs--such as gated clocks, ASIC memories, DesignWare components and design constraints--must be translated automatically and mapped into appropriate boards and FPGA resources. For that to be done efficiently and correctly, the multi-FPGA implementation software must have an intimate knowledge of the targeted prototyping board.

Similarly, the FPGA board itself must not only be of highest quality and reliability, but also must be flexible and extensible enough to handle every ASIC design. Because the prototyping board verifies high-value ASIC designs, it must be equipped with extensive self-monitoring and self-test capabilities to ensure that all detected bugs are really design bugs and not merely failures of the prototyping board.

Juergen Jaeger (juergen@synplicity.com) is senior director for ASIC verification marketing at Synplicity Inc. He studied electrical engineering and computer science at institutions in Germany.