Low-power designs have raised the bar on the verification effort. Designs optimized for power often employ complex design techniques that introduce their fair share of new bugs that are hard to track and fix. A single undetected power-management bug can result in functional failures manifesting in silicon.

Tight product development schedules have put immense pressure on verification teams to hunt for these bugs. The verification complexity involved with low-power designs has led to a quest to simplify and automate the bug-finding process. This is where assertions come into the picture.

Assertions themselves have been well-known to verification engineers for some time now. Assertions can be expressed in testbenches in languages such as SystemVerilog. Functional simulators monitor specified assertions and generate messages indicating whether they have passed or failed. A failed assertion is an indication of a design problem. Assertions can therefore serve as a valuable tool to help pinpoint the type and location of functional failures early in the design cycle. Assertions that find bugs at the RTL stage can potentially save months of verification time or even help avert a potential respin for bugs that go undetected until they manifest themselves in silicon.

Power of assertions

Low-power designers can effectively use the power of assertions to detect hard-to-find bugs and design problems. Assertions can be manually generated, but user-instantiated assertions need to be design-specific and complete. A single missed assertion can potentially lead to a missed bug. Automation can reduce this risk.

Knowledge of low-power design techniques can drive EDA toolsí automatic generation of assertions for such designs. For example, in low-power design the clock should not toggle for a powered-down domain. In a design with pass transistors, ungated clocks to powered-down domains can cause battery drain. Clocks consume a lot of power, and eliminating unwanted clock toggling is the first and most effective way to curb power dissipation in a design targeted for low power. Because it is a general principle of low-power design, such an assertion can be built into the tools.

Value of automated assertions

To correctly identify bugs or design problems, assertions must be written and triggered at the leaf levels of the design. This is not a trivial automation task. Most low-power simulators expect the verification engineers to explicitly specify all the assertions and then instantiate them appropriately for the target design. This is a cumbersome and error-prone activity.

Assertions can be written to verify RTL and gate-level designs. Far more assertions are required to cover all the leaf-level pins in a design than for the RTL.

As an RTL design gets synthesized, signal names go through a mapping process, and there may be many leaf-level pins at the gate level associated with a single leaf-level pin at RTL. Assertions written for RTL typically need to be modified for gate-level simulation, because synthesis scripts change signal names when transforming RTL to a gate-level description of the design.

Manual specification of assertions at RTL implies manual respecification at the gate level. During the early stages of design, it is typical for the RTL to change frequently before it is frozen. Any RTL that was synthesized will need to be resynthesized and the corresponding gate-level descriptions will change, requiring a manual rewrite of assertions at both levels.

IP perspective

In addition, designers of intellectual-property (IP) blocks typically struggle with assertion generation, because they canít contemplate all the possible ways the IP block will be power-managed when instantiated in a system-on-chip (SoC) design. Therefore, assertions must be design specific. Manual specification doesnít lend itself to a scalable verification environment for low-power designs.

Automated generation and instantiation of design-specific assertions is the most efficient way to complete verification of low-power designs. Such a methodology unburdens the time-strapped verification team from writing and maintaining assertions. It also creates a scalable and reusable low-power verification methodology. IP vendors no longer need to worry about all the possible ways their blocks will be used in SoC designs. A design that goes through a series of engineering change orders also benefits from the power of built-in, automatically generated assertions.

Verification of low-power designs does not have to be an intractable challenge. Verification teams need not be stressed. They can now utilize the power of built-in, automated assertions to quickly detect and debug hard-to-find low-power bugs. Verification productivity and accuracy can be dramatically increased with the aid of built-in and automated low-power assertions.

About the author

Krishna Balachandran (krishnab@synopsys.com) is director of product marketing for low-power verification products at Synopsys. He holds a masterís degree in computer engineering from the University of Louisiana and completed the executive MBA certification program at Stanford University.