Cooley, moderator of the E-Mail Synopsys Users Group (ESNUG), sent a questionnaire to participants in the March 2004 DVCon. Some 137 engineers answered the 11-point questionnaire, yielding over 400 pages of responses, Cooley said. The DVCon trip report presents the statistical response to each question along with detailed comments from the engineers.

Among the findings that Cooley found significant: Mentor Graphics' ModelSim is the most popular simulator, one out of three verification engineers plan to use SystemC, most engineers don't use third-party code coverage or lint tools, most don't use assertion checkers, and an overwhelming majority believes specialized verification languages will disappear.

The data on Verilog and VHDL simulation showed that 49 percent of engineers are using Verilog only, 45 percent are using both languages, and only 6 percent are using VHDL only. Cooley noted that the survey included many respondents from Europe and Asia, where VHDL is strongest.

Asked which Verilog or VHDL simulators they currently use, 41 percent chose ModelSim, 34 percent Synopsys VCS, and 23 percent Cadence NC-Verilog. After Cadence's simulation offerings came Aldec with 7 percent.

While designers have been vocal in their hatred of SystemC, Cooley commented, it's a different story in the verification world. The DVCon trip report showed that 32 percent of respondents plan to use SystemC in the next 6 months. Of these, nearly all will use it for high-level modeling and verification as opposed to design.

"SystemC smartened up and stopped trying to be an extremely painful design language that just evoked Pavlovian fear responses from experienced design engineers," Cooley wrote. "Instead, the verification folk use SystemC in a niche where it peacefully and non-threateningly thrives as a speedy architecture and high-level modeling simulator."

Engineers aren't immediately flocking to SystemVerilog, the report found. Just 21 percent of respondents said they'd use SystemVerilog in the next 6 months. Of these, 63 percent said they'd use it for verification, and 32 percent for both verification and design.

Meanwhile, there is doom and gloom about specialized verification languages such as Vera and "e" in the report. While 28 percent of respondents use "e" today, and 26 percent use Vera, 81 percent of respondents said they think specialized verification languages will be dead in five years.

There's more optimism about assertion languages, where 53 percent of users plan to use assertions on their next project. The most popular choice is Accellera's Sugar language, favored by 34 percent of respondents.

The DVCon trip report paints a bleak picture for some HDL simulation add-on tools. It found that 75 percent of respondents use code coverage tools that come with simulators, rather than third-party products. 60 percent use built-in lint tools. But in the debugging category, Novas products are used by 45 percent of respondents.

The report found that 83 percent of respondents "hate" graphical design entry tools. Also disliked are hardware/software co-verification tools, used by just 12 percent of respondents.

What the report called "bug hunter tools" from vendors such as 0-In, Jasper, @HDL, Real Intent, and Averant are used by only 30 percent of respondents. 0-In is the clear favorite of those who do use such tools. Yet another category avoided by most respondents is accelerators and emulators. 52 percent of respondents don't use them, and 20 percent use home-brewed FPGA solutions.

74 percent of respondents do use formal equivalence checkers, with Cadence's Verplex leading the pack at 38 percent. The report also found that 52 percent use verification IP, but Cooley acknowledged the results are skewed because he accidentally left Denali off the questionnaire.