Accellera's decision to pursue SystemVerilog standardization through the IEEE's corporate standards group, rather than the existing IEEE 1364 committee, has raised concerns about the development of incompatible language standards. Karen Bartleson, Accellera secretary, said the choice was made because the corporate standards group has an "entity" model of one vote per company, versus the "individual" model that prevails in other IEEE working groups, including IEEE 1364.

The entity model will permit a faster standard, she said. "The entity balloting model completely levels the playing field," she added. "There is no stacking of votes allowed." She noted that Intel's Johny Srouji, who heads Accellera's SystemVerilog design modeling group, chairs the IEEE p1800 study group that will standardize SystemVerilog.

Insiders say some Accellera members were concerned about the number of votes that Cadence Design Systems and Verisity have in the IEEE 1364 group, which has a "one individual, one vote" policy. Although they proclaim support for SystemVerilog now, Cadence and Verisity were skeptical in the past.

Edward Rashba, manager of new technical programs for the IEEE Standards Association, said the corporate standards group offers quick initiation and development, clearly defined rules, paths to international standards bodies, a competitive cost structure, and experienced professional support. But only one standard has so far gone through the relatively new process, he noted.

Harry Foster, chair of Accellera's formal verification technical committee, said his committee has approved the Property Specification Language (PSL) 1.1 specification and that it's now under review by the Accellera board.

Geoffrey Coram, chair of the Verilog-AMS committee, noted that the Verilog-AMS Language Reference Manual (LRM) version 2.3 is under review. It adds extensions for compact models.

Work also continues on the Open Verification Library (OVL) of assertions, said David Lacey, chair of the OVL committee. He noted that a PSL version of Verilog and VHDL libraries is available, a testbench component is being prepared for release, and the first version of the LRM is near completion. A SystemVerilog version of the library is upcoming.

Vassilios Gerousis, chair of Accellera's technical committees, reviewed progress of the Open Kit (OK) initiative, which seeks to standardize process design kits. He said that working groups are now developing a standard symbol set for design capture, physical design rule formats and naming conventions, and electrical datasheet formats.

Gerousis also presented Accellera's Technical Excellence award to John Havlicek, principal staff scientist at Freescale Semiconductor, who has worked on the semantics of SystemVerilog assertions and on synchronization of PSL with SystemVerilog assertions. The award, Gerousis said, honors individuals involved in Accellera standards efforts.

Accellera's Vassilios Gerousis (right) presents Technical Excellence Award to Freescale's John Havlicek

Accellera vice president Shrenik Mehta reviewed 2004-2005 goals for the organization. He said these include financial and resource support for IEEE p1800, a continued effort on SystemVerilog errata, the next phase of PSL, and the publication of new standards such as Verilog-AMS 2.2.