The purpose of the ONFi is to simplify the integration of NAND flash memory into consumer electronic products, computing platforms and other applications that utilize solid state memory as a mass storage medium.

Evatronix specified that the updated NAND Flash Controller IP is available now for implementation in any FPGA or ASIC technology. The IP core is delivered as an RTL source code with a set of scripts and macros for simulation/synthesis support or as an FPGA netlist targeted to the latest programmable devices.

The NAND Flash controller IP is complemented by a dedicated software driver that supports hardware features of the controller.

In parallel, Evatronix announced it will hold free technical seminars at IP-ESC early December in Grenoble, France, with speakers from Samsung Semiconductor and Micron.

Seminar sessions will notably discuss the new SuperSpeed USB 3.0 standard, as well as benefits and techniques of developing a USB Mass Storage application based on a SuperSpeed USB 3.0 peripheral controller.

Other seminars will also discuss NAND flash memory in embedded applications using SD, e-MMC and bare NAND Flash or explore directions that a SoC designer may take while building a verification environment for his application.

More details are available here