The .lib format, with its table of numbers, has been the de facto industry-standard timing format for over a decade. Most of the electronic products in our lives touched both .lib and its table at some point. However, that table of numbers, also called a nonlinear delay model (NLDM), is nearing the end of its evolution, a casualty of the drive to sub-130 nanometer silicon technology.

This is especially true in low power design styles that incorporate two or more "islands" of logic, each running at a different operating voltage. Traditional library cell characterization that accurately covers a wide range of operating voltages can be prohibitively time consuming. There are, on the other hand, alternatives that deliver accuracy without an inordinate increase in characterization time.

Two newer approaches, the Scalable Polynomial Delay Model (SPDM) and Effective Current Source Model (ECSM), are currently vying to replace the NLDM model. Both have the ability to predict nanometer timing across a range of supply voltages. Overall, ECSM is technically superior and is expected to be the new standard.

SPDM is a mathematical expansion — basically a polynomial with multiple coefficients relating timing to a variety of inputs. In theory, SPDM can be used to model delay variation due to environmental factors such as voltage and temperature.

The difficulty is fitting the actual non-linear behavior using a polynomial with a limited number of variables and corresponding coefficients. The physical world is so non-linear that it is very difficult to obtain good accuracy with SPDM.

In practice, the extreme effort to characterize real silicon to SPDM has made it unpopular. Sophisticated optimization algorithms are required to perform curve-fitting of the SPDM polynomial to simulation data, and the accuracy and turn-around-time of the library creation is limited by the quality of the optimization algorithms.

The alternative, ECSM, is much simpler. Rather than a mathematical abstract, ECSM is a physical model patterned after the actual construction of transistors. Like SPDM, it accurately models nanometer effects in silicon; unlike SPDM, ECSM is easy to characterize.

ECSM models are available today from major library and silicon suppliers like Artisan and TSMC, with off-the-shelf characterization software available from both Magma and Cadence. Commercial chip design software which supports ECSM is available from Cadence and Magma. Also unlike SPDM, over 100 working chip designs have taped out using ECSM.

In a landmark study done by Artisan Components, a 90-nanometer silicon technology was characterized at three different voltage points in a single ECSM library. Timing was then measured at 270 different combinations of supply voltage, slew and loading. Both the average and the standard deviation of error compared to Spice were well under 1 percent, and the largest single outlier was 5.4 percent.

Low power designs at 90 nanometers have introduced new challenges for timing and delay calculation to support design styles that include multiple VDD supplies to single instance (level shifters), cells used with different supplies (voltage islands), and lower supply voltages to save power, but with increased sensitivity to IR drop and signal integrity. ECSM meets all of these requirements

Advantages of ECSM include:

• Accurate modeling of nanometer timing, including supply voltage variation, easy characterization.
• Broad library support from vendors such as Artisan, TSMC and Virtual Silicon.
• Characterization software from Magma and Cadence.
• Chip design software in Cadence SoC Encounter and Magma Blast Fusion.
• Production proven with over 100 tapeouts.

As such, ECSM can be represented as a property field inside of a .lib file. This means that existing software tools which do not support ECSM but do comply with the .lib standard are ECSM-compatible, although are not as accurate. Incorporating ECSM within the .lib files used by Cadence SoC Encounter and Magma's Blast Fusion has not created any problems. This is a good indication that other software developers will have a similar experience.

Timing remains the centerpiece of digital chip implementation. The behavior of silicon changes from geometry to geometry. So, too, must the modeling of timing evolve. With practical innovations such as ECSM, design teams can retain predictability for many more years of world-changing electronics.

Premal Buch is general manager of the Analysis Business Unit at Magma Design Automation. Wei-Jin Dai is vice president for the Encounter platform at Cadence Design Systems.