SAN JOSE, Calif. — Hardware acceleration startup Tharas Systems Inc. has released a Verilog four-state logic simulation add-on to its Hammer hardware accelerator.
The company announced the new capability allows the Hammer 100 to detect and propagate 4-logic — 0, 1, X, Z — similar to a Verilog software simulator.
The company explained that traditionally, engineers use four-state capability in Verilog to pessimistically model design elements. The technique helps uncover errors in reset logic, random initialization, bus conflicts and uninitialized registers and issues in ATPG-based verification.
Engineers couldn't use the technique in hardware assisted verification as only two states — 0 and 1 — were supported.
The company said Hammer 100 now offers functionality similar to a software simulator. The four-valued accelerated simulation capability is backward compatible with Hammer 100 hardware.
Tharas said the four-state capability is $20,000 add-on for Hammer 100 version 4.0. It is also available through T-FORCE, Tharas' Flexible on-demand rental collaborative environment program.
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