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EE Times - Silicon Engineering Archive Silicon Engineering Archive


January 2003

  • <B>Commentary:</B> Novel strained-silicon substrate simplifies SOI fabrication
  • Prepping high-V devices for SoC integration
  • Models for high-voltage transistors in a standard CMOS process
  • Integration brings CPU into analog design
  • Testing next generation wireless-LAN RFICs takes some doing
  • SoC silicon is first-time success following simulation and validation of novel array processor
  • The Challenges of 0.18um Mixed Signal Design
  • SoCs find a home in low-end embedded design

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