United Business Media EE Times


Search

HOMEMARKET INTELLIGENCE UNITFORUMSDESIGNNEW PRODUCTSCAREERSBLOGSCONTACTEVENTSSIGN UP!RSSMost Popular contentTrusted Sources

 

TSMC's Hu sees earlier entry for FinFET
Print this article Email this article Reprints RSS Digital Edition

EE Times


San Francisco - Once deemed a down-the-road technology, FinFETs could instead see use as early as the 65-nm process node, one of their pioneers believes.

Calvin Chenming Hu, chief technology officer of Taiwan Semiconductor Manufacturing Co. Ltd., said the industry's failure to prove out a reliable high-k gate stack that limits leakage current for planar transistors could be one reason to go to three-dimensional structures early.

Hu, for many years a distinguished researcher at the University of California at Berkeley before joining TSMC in 2001, helped a Berkeley team develop prototypes of the FinFET, a vertical transistor structure with a fin-like channel.

FinFETs have been looked upon as a way to scale down to 10-nanometer gate lengths after planar transistors ran out of steam.

But Hu said that the need to optimize transistor performance and leakage current could drive an early use of FinFET devices.

"I think the FinFET is going to be used, but not wholesale," Hu said. "There won't be a chip where you look in and every transistor is a FinFET. No, it will be used selectively where the performance requires it. I think it could come as early as the 65-nm node."

That assessment is ahead of most other predictions. At IBM and other companies, the first introduction of the FinFET is put at the 45-nm node or later, largely because the EDA tools needed for layout would have to be altered.

But as problems with gate oxides multiply, including setting the threshold voltage and dealing with carrier mobility, enthusiasm for the FinFET has increased.

At the 2002 International Electron Devices Meeting, Advanced Micro Devices Inc. announced the world's smallest double-gated FinFETs at the time, with gates measuring just 10 nanometers.

TSMC engineers described a complementary pair of "Omega-shaped" FinFET transistors on a 25-nm process at the same 2002 IEDM. The 25-nm process node is scheduled for production in 2009.

And at June's Symposium on VLSI in Kyoto, Japan, Intel said that further progress with a trigate transistor structure with 30-nm critical dimensions could come into use as early as 2007. The vertical trigate transistor structure provides high drive current, low leakage current and a minimum of manufacturing difficulties, Intel said.

http://www.eet.com






  Free Subscription to EE Times
First Name Last Name
Company Name Title
Email address
  Click here for your Free Subscription to EETimes Europe
 
CAREER CENTER
Looking for a new job?
SEARCH JOBS
SPONSOR

RECENT JOB POSTINGS
CAREER NEWS
DoD Recognizes University Scientists For Basic Research
Annual awards to university faculty to conduct next-generation research projects were announced this week by the Defense Department.

For more great jobs, career related news, features and services, please visit EETimes' Career Center.



All White Papers »   

 
Education and
Learning


Learn Now:












Home | About | Editorial Calendar | Feedback | Subscriptions | Newsletter | Media Kit | Contact | Reprints|  RSS|   Digital|  Mobile
Network Websites
International
Network Features




All materials on this site Copyright © 2010 TechInsights, a Division of United Business Media LLC All rights reserved.
Privacy Statement | Terms of Service | About