The 130-nm node is likely to have a relatively long life as mixed-signal designers cling to the 1.2 V power supplies needed for analog functions, Vucuverich said here at a Fabless Semiconductor Association seminar. The 1V rating for most 90-nm offerings is not attractive for analog-intensive designs, he said.

For digital-dominated designs, graphics companies such at ATI, Nvidia and others are moving quickly to 65-nm design rules — in some cases even faster than vendors of high-performance microprocessors, NAND flash and DRAMs.

"Once designers figure out the parasitics and how to deal with power issues, they go to 65-nm quickly," he said Thursday (April 7).

There are few materials changes from the 90- to 65-nm nodes, with high-k, interconnect and inter-metal dielectrics roughly the same. Moreover, the techniques employed at the 90-nm node to keep leakage currents under control can be adapted to the 65-nm node, he said.

Asked about mask costs, Vucuverich said the industry is working to differentiate between the crtical and non-critical mask features, pointing to research by Mark Mason at Texas Instruments Inc. and Karen Maex at IMEC, the Belgium-based Interuniversity Microelectronics Center. The use of more optical proximity correction at the 65-nm node will not slow down most companies, and the 193-nm scanners are nearly the same, he added.

Vucuverich said the industry badly needs to shift to richer models that include support for statistical timing, power, and yield predictions. Support for statistical timing is being implemented now at leading integrated device manufacturers for both high-performance and high-volume products, he said.

While IDMs can accomplish the shift by sharing information between design process, modeling and manufacturing engineers, he said foundries sometimes hit a wall created by "the sanctity of information" between the various engineering disciplines.

"We have to move away from static libraries. And extraction, modeling and simulation needs to be a lot more integrated," he said. The use of multithreading will allow parallel-computing techniques to be applied to the more complex design models, he said, adding that many current EDA tools can be readily adapted to statistical timing techniques.

The shift to statistical timing will have the immediate effect of reducing design margins that leave a great deal of performance on the table. "The window can be much narrower, and more aggressive," he said.

The industry has been weighed down by relatively poor first-time design success rates, he said, quoting data from analysis firm Collett and Associates. In 2003, only about one-third of the 130-micron designs achieved first-time success. After the third iteration, only 60 percent of the designs worked, he said, attributing hard-to-detect in the designs for the low rate of improvement. After three failures, many designs afflicted with "really hard problems" are declared disasters and abandoned altogether, he said.