Presenting a paper at the SPIE Microlithography Conference here Tuesday (Feb. 22), Capodieci argued that irregular features within designs works against automated "layout printability verification" in an age where process variability has become prevalent.

More and more, Capodieci said, yield ramps can be accelerated by using regular, standardized circuits and features, a process he dubbed "design layout regularization." Incorporating only regular structures, Capodieci said, would enable a holistic view that would improve designs and printability.

Capodieci showed data from a recent analysis of a design that showed that three types of pitches were used most often and several others used much less frequently. Elimination of these irregular pitches, he argued, is necessary for improving manufacturability.

"Going towards 45 nanometer, our goal is to eliminate these other types of pitches that do not need to be there and can impact yield," Capodieci said. He called for regularity in device designs not only at the layout level, but at the circuit level as well.

Capodieci refuted the conventional notion that the strict use of regular circuits would cause a substantial penalty in area. He said several papers presented at last year's Design Automation Conference point to the viability of regular circuit fabrics — configurable bricks that are a fixed size and very easy to manufacture — without substantial area penalty.

According to Capodieci, chip makers are increasingly turning to two-dimensional, image-based design rule checks to identify potential yield-limiting factors. The goal for the industry at the 32-nm node, he said, is to try to make layout more one-dimensional, enabling the identification of irregular structures for systematic regularization of layout the level of place-and-route.

For the past 10 years, Capodieci joked, the constant evolution of resolution enhancement technology has remedied lack of intelligent designs. Lithographic-driven design-for-manufacturing (DFM) is now a well-established practice at the 65-nm node, he said. The continuing evolution of DFM depends on a drive toward more and more regular layouts, he said.