Synplicity (Sunnyvale, Calif.) said the methodology is being offered as a means to address the challenges designers face when using protected IP in design flows, which are often composed of tools from several different EDA vendors. The proposed methodology supports tool interoperability and the underlying technology allows IP providers and EDA vendors to deliver solutions to their customers that provide the flexibility and security necessary for an industry standard to emerge, according to Synplicity.

Synplicity is a provider of FPGA synthesis tools, but the methodology works for ASIC flows as well, according to the company.

"There are two impacts," said Andrew Dauman, Synplicity's senior vice president of worldwide engineering. "The methodology can greatly reduce the amount of work the IP vendors and tool vendors need to do to support IP flows. And, it greatly improves the user experience with adopting IP, because less is required to negotiate contracts to get access to the IP."

Some EDA companies have attempted to offer their own proprietary IP encryption schemes, but, according to Synplicity, those efforts failed because proprietary schemes do not satisfy user needs for interoperability between tools from multiple vendors. The proposed non-proprietary methodology will allow IP vendors to create a single version of the encrypted data that can be used by tools from multiple EDA vendors, the company said.

The methodology utilizes openly available, government-approved encryption methods combined with an encryption embedding mechanism proposed by Cadence Design Systems Inc. for the next revision of IEEE 1364-2005, Synplicity said. The methodology also permits IP vendors to choose how far encryption persists through the design flow and includes the option of encryption all the way to the semiconductor, the company said.

Some IP customers have already come forward with support for Synplicity's proposed methodology.

If users want a strong commercial IP market, vendors must be able to protect their IP, according to Callan Carpenter, vice president of business development for IP provider PLD Applications. Given the limitations of proprietary encryption flows, Carpenter hopes that all major EDA and silicon vendors will support the Synplicity proposal. "It's a no brainer from an IP perspective," he said.

There is "absolutely" a need for a standardized IP encryption methodology, said Sujoy Mitra, senior manager in charge of IP core delivery at Xilinx Inc. "This is a big issue for Xilinx," he said. "The fact that we don't have one scheme that works with everyone, that all IP vendors can deploy, really makes it a big problem for us."

In a statement issued by Synplicity Monday, Hal Barbour, president of IP vendor Cast Inc., said his company has seen several mechanisms for protecting IP cores come and go over 13 years in the business, but that Synplicity's approach appears to be a step up.

"It should simplify product deliveries and sales evaluations for IP providers, and lead to greater choice and flexibility for IP users," Barbour said. "We're enthusiastic about adopting it for Cast cores and expect that other IP firms and more EDA companies will join in soon."

Synplicity plans to host a breakfast panel the July 25 at the 2006 Design Automation Conference here to discuss this open IP encryption flow and methodology. Panel members include representatives from ARM, Cadence, Lattice Semiconductor, VSI Alliance (VSIA), Xilinx and Synplicity.

A more detailed story about Synplicity's proposed IP encryption methodology appears in this week's EE Times print edition.