Rothemund's "scaffolded origami" involves folding long, single strands of DNA into arbitrary two-dimensional shapes using a raster fill technique. DNA "helper" strands fold the scaffold into the proper formation. Design and synthesis are so simple that even a high school student could do it, he said, but that doesn't mean some automated CAD tools aren't needed.

"In making these shapes, I did a lot of things manually," Rothemund said. "I used the computer as glorified graph paper and determined the architecture of the design by hand." There's a lot of room for optimization in the design of DNA sequences, he noted.

The potential benefits of DNA self-assembly were further demonstrated in a paper presented by Chris Dwyer, assistant professor of electrical and computer engineering at Duke University. His work involves shaping DNA strands into self-assembled grids that could potentially produce patterns relevant to logic circuitry.

Dwyer's price is hard to beat. His paper said he was able to generate 1012 to 1014 structures for a materials cost of $40, with approximately 60 percent yield. This can be done in a 60-microliter reaction volume. "The technology is here, and it's time to start thinking about architectures and systems," Dwyer said.

His research group currently has tools for cluster-based sequence optimization, layout and assembly. Dwyer's "wish list" includes yield-aware design optimization, refined device models and better, automated full-custom layout.

CAD for lab-on-a-chip
One of the most futuristic nanodevices is the biofluidic microchip, which includes lab-on-a-chip devices that can take a fluid sample and run a biochemical analysis. Portable analysis is the driving need, said Tamal Mukherjee, professor of electrical and computer engineering at Carnegie Mellon University.

"We eventually want to get to something like Mr. Spock and his tricorder," he said. With a lab-on-chip, Mukherjee noted, a user might be able to identify the virus that's making a child sick, transmit the DNA sequence to a pharmacy and get the correct treatment right away.

Some lab-on-chip devices transfer droplets using electrical fields. Others use pressure or voltage to move fluids through channels. Subsystems handle functions such as injection, mixing, separation and reaction. But it's a lot like system-on-chip design, Mukherjee said, in that it involves a limited set of library elements that are replicated many times.

Lab-on-chip designers must size microfluidic channels and determine electrokinetic drive voltages. The designers perform simulation, optimization, placement and routing. Mukherjee described a hierarchical decomposition approach that uses "Spice-like" code to assemble the design. It uses a library of parameterized models for wells, mixers, reactors, injectors, separators and splitters.

In addition to simulation and optimization, these models can be used to perform physical synthesis. Properties and constraints are used to floor-plan subsystems, determine placement of components such as wells and route subsystems to wells.

"We're focused at the circuit level," Mukherjee said. "We still haven't addressed architecture or protocol optimization."

Small world after all
From a CAD perspective, said Seth Goldstein, associate professor of electrical and computer engineering at Carnegie Mellon University, it's not so much the technology that's important — it's the revolution in system design made possible by the availability of massive numbers of nanoscale devices.

Because we'll have so many devices, Goldstein said, it's inevitable that reconfigurable computing will be needed to speed time-to-market and reduce manufacturing costs. Asynchronous architectures will reduce power, solve timing problems and aid defect tolerance. Spatial computing, which optimizes for wires at the expense of using more computational nodes, will reduce power and wire delay.

This scenario calls for significant new EDA developments, including very high-level synthesis and tools that can handle asynchronous design. "There's no reason at all that humans should be involved in the verification process from models on down," Goldstein said.

Such statements make it clear that the real design challenge for nanotechnology is not RLC modeling for carbon nanotubes, but figuring out how to take billions of devices and build something useful quickly.