The biggest advantage of IC design at 65 nanometers, 45 nm and below may not be gate capacity or power savings after all. It may be the ability to design inefficiently with respect to transistors, discovering new methodologies and architectures in the process.

Granted, "design for inefficiency" doesn't sound like a great slogan. But let's ponder this question: What could designers do if they had so many available transistors and logic devices that using each one with maximum efficiency was no longer a consideration?

For one thing, they could use high-level, automated, C-language synthesis to design chips quickly. Yes, there would be some area inefficiency and lower gate utilization, but for many applications that wouldn't be a problem at the nanoscale level. As long as power and performance targets are met, the most important thing is getting a new product into the hands of consumers before the competition.

They could also consider asynchronous architectures. At the recent International Conference on Computer-Aided Design (ICCAD), Seth Goldstein, associate professor of electrical and computer engineering at Carnegie Mellon University, noted that asynchronous circuits remove the problem of timing closure, eliminate global clocks and tolerate parametric variation. They may take two to six times the area of synchronous circuits, but at the nanoscale level, Goldstein said, "all of a sudden we have those devices."

Programmable architectures of all kinds may flourish at 65 nm and below. FPGAs, which will always be much more area-inefficient than ASICs, will have enough gate capacity for a growing number of applications. Reconfigurable architectures that can be quickly programmed from a high level of abstraction may become more feasible. As Goldstein noted at ICCAD, reconfigurable circuits provide defect tolerance, reduce manufacturing costs and shorten time-to-market.

At the circuit level, placing transistors and contacts on a virtual grid is one way to reduce the impact of process variability. Simple, regular layouts that ease design and manufacturing will be easier to implement if there is less concern about using up space on the die.

The leading-edge users who churn out the first 65-, 45- and 32-nm chips probably will be concerned about squeezing the maximum out of every logic device. But the wave that follows-the mainstream-may be much more interested in the quick-and-dirty design approaches that become possible when they don't have to worry about "wasting" transistors.

The latter approaches will open a new chapter in IC and systems design. They will also present the next set of challenges for the EDA community, including tools for high-level synthesis, asynchronous design, and programmable and reconfigurable architectures. RTL design as we know it will fade as silicon shrinks. By the time true nanotechnology IC design rolls around-with carbon nanotubes, single-electron transistors, DNA self-assembly and the like-the problem will be one of designing something useful very fast from incredibly cheap and abundant devices.

Richard Goering is managing editor of Design Automation for EE Times