A classic example from ISSCC 2006 is a paper presented by a research group led by Bevan M. Baas - Assistant Professor at University of California, Davis. This paper introduced an experimental chip called an Asynchronous Array of Simple Processors (AsAP), which is of particular interest for DSP Applications. (Even though "AASP would be the correct acronym, the team named it "AsAP" because they liked the "as soon as possible" connotation.) A few of the AsAP's more notable points are as follows:

• The latest version has 36 programmable processors on one chip.
• Each processor has its own local oscillator and operates fully asynchronously with respect to the other processors.
• The processors are connected using a reconfigurable mesh network.

The current test chip, which is implemented in 180nm TSMC CMOS, runs at 475 MHz (possibly the fastest programmable processor designed in a university), and each processor consumes an average of only 32 mW while actually running applications (see notes below).

The idea behind the AsAP is for each processor to be as simple yet as powerful as possible. Thus, each processor has a local memory that can store 64 instructions and 128 data words; also each processor – which operates on 16-bit fixed-point data – contains a 16-bit ALU, a 40-bit accumulator, and can perform a 16-by-16-bit multiply in a single cycle.

As example applications, a JPEG encoder can run on a chip containing only 9 processors; while an 802.11a/g wireless LAN transmitter can run on a chip containing only 22 processors; both applications can run simultaneously in a chip containing 31 processors; and so forth.

Each processor on this experimental chip is constructed from around 230K transistors and occupies only 0.66 mm^2. If this exact design were scaled to the 90nm technology node, a 13mm x 13mm chip could contain over 1000 processors, operate at almost 1 GHz, have a peak throughput of 1.0 TeraOp/sec, and dissipate only 8 Watts (plus leakage).

A key feature of the AsAP is that each processor has its own oscillator and is clocked independently. This allows each processor to be run at the minimum speed necessary to perform its particular task (processors completely shut off when they are idle). The team has designed a special circuit to connect processors to each other that places no restrictions on the transmitting or receiving processors' clocks. The clocks can be running at different frequencies; the frequency of each clock can be independently adjusted depending on each processor's local workload; clocks can be halted and restarted; and through all of this data is guaranteed not to be lost or corrupted.

Of particular interest is the fact that having local clocks for each processor - and having the processors communicate between themselves – asynchronously – means that the AsAP is inherently scalable, and it will be easy to create new devices containing more processors.

For more information, contact Assistant Professor Bevan M. Baas, Dept. of Electrical and Computer Engineering, 2037 Kemper Hall, University of California – Davis, CA 95616-5294, email him at bbaas@ece.ucdavis.edu, or visit his website at www.ece.ucdavis.edu/~bbaas/.