San Jose, Calif. -- An open-source architectural-description language from Brazil that promises to take SystemC in new directions was outlined at the North American SystemC User's Group (Nascug) meeting here last week. SystemC may also extend its reach with a synthesizable subset and a new proposal for an analog/mixed-signal version of the language, other presenters said.

Rodolfo Jardim de Azevedo, assistant professor at the Institute for Computing at the State University of Campinas (Brazil), presented ArchC as a language that provides a fast and easy way to model processors. Built on top of SystemC, ArchC can generate simulators and assemblers. Support is available now for processors including MIPS, Sparc v8, PowerPC and 8051, with ARM support slated for March.

"There's a whole set of tools yet to be defined to go on top of SystemC, and this [ArchC] is an example," said Nascug chairman Jack Donovan. "Everyone is trying to understand ways to do faster modeling."

With ArchC, Azevedo said, a user could design a new processor or add instructions to an existing one. Further, he said, ArchC can help designers of multiple-processor systems-on-chip (SoCs) simulate and debug their designs. With ArchC's GDB interface, for example, a user could open multiple GNU debugger windows for multiple processors on an SoC.

ArchC can produce an instruction-set simulator or cycle-accurate interpreted simulator with a GDB interface. It can also produce a compiled simulator that claims speeds of up to 200 million instructions per second. This, said Azevedo, allows "real programs" to run on the processor model. ArchC also supports Linux operating-system call emulation and can run binary code directly from the GNU C compiler.

Azevedo said that ArchC started as a research project at his university, with funding from the government of Brazil. Originally, he said, the project had a "processor centric" view, but that's now changed to a "platform view" with support for multiple-processor SoCs.

An architecture description in ArchC is divided into two parts. In an instruction-set architecture description, the designer provides such details as instruction names, formats and sizes. In the architecture-elements description, the designer lists such resources as memories, word size and pipeline structures. Abstraction levels vary according to the level of accuracy the user wants in simulation.

The behavioral part of the processor model is "pure SystemC," Azevedo said, noting that ArchC uses the SystemC transaction-level modeling library standard.

Why open source? "When you're designing a processor, you need a huge infrastructure," Azevedo said. "You need a compiler, assembler and instruction-set simulator. We're trying to define that with an architectural-description language and put it in the public domain."

ArchC 1.6, along with processor models, an assembler generator, compiled simulator, GDB interface and precompiled programs, is available for free download at www.archc.org.

While processor modeling is one way to extend SystemC, analog design would be another significant new direction. Pat Sheridan, executive director of the Open SystemC Initiative (OSCI), said that an analog/mixed-signal working group has been proposed by Philips and STMicroelectronics. The proposal is under review by the OSCI steering group, he said.

Sheridan also noted that OSCI intends to bring its transaction-level modeling (TLM) and SystemC Verification standards to the IEEE this year.

Adam Rose, verification technologist at Mentor Graphics Corp., noted that the current TLM 1.0 standard establishes a common transport mechanism. It thus tells how transactions can be moved back and forth, but not what the transactions are or what to do about them when they're moved, he noted.

Thus, said Rose, the TLM working group is looking at two further steps. One is a set of standard bus-modeling application programming interfaces, which will help determine what transactions get moved. Another is a set of standard configuration-and-control APIs, which will show how to control and analyze the transactions that are moving through the models.

Andres Takach, acting chairman of OSCI's synthesis working group, said his group has developed a draft that defines a synthesis subset. It uses C++ as a base, allows a variety of data types and supports modules, events, signals and ports.

Nascug also featured tutorial presentations, including several from users. Engineers from Freescale Semiconductor Inc. showed how they use SystemC in an RTL design flow. An HCL Technologies engineer discussed the reuse of SystemC transaction-level models. An engineer at Sonics showed how it simplifies SystemC models for hardware/software co-validation.