After years of working at the register-transfer level, chip designers and verification engineers are warming up to a new approach that may represent the next step up in abstraction. But it's not a wholesale methodology shift. Instead, it's a modeling technique that uses function calls, rather than signals or wires, to communicate between modules.

This approach is called transaction-level modeling, and it's not really new--in one form or another, TLM has been around for years. What is relatively new is the emergence of two standard languages, SystemC and SystemVerilog, that can support it, as well as increasing tool and intellectual-property (IP) modeling support. But the infrastructure is nascent, and there are still large gaps in standardization and tool support.

"We think TLM is the next level of design and verification abstraction in EDA, and we are seeing major customers starting to adopt it right now," said Stuart Swan, senior architect at Cadence Design Systems Inc. and a member of the Open SystemC Initiative (OSCI) TLM working group. TLM, he said, is "by far the most active area" in SystemC standardization and usage.

But what is TLM? Aside from the basic idea of communication through function calls that represent transactions, there is no clear agreement on just what TLM encompasses.

"When we go into customers, everyone's concept of TLM is different," said Brett Cline, vice president at Forte Design Systems, which recently introduced a SystemC TLM synthesis capability.

OSCI seems to have the most liberal interpretation. OSCI includes several levels of abstraction under TLM, including Programmer's View (PV), which contains no timing; Programmer's View with Timing (PVT), which adds timed protocols and can analyze latency or throughput; and Cycle Accurate, which is accurate to the clock edge but does not model internal registers.

From an OSCI point of view, pretty much everything above RTL can be considered TLM, said Pat Sheridan, OSCI executive director and the director of marketing at CoWare Inc. But the way most users think of TLM appears to include just the untimed (PV) and cycle-approximate (PVT) styles of modeling.

Frank Ghenassia, director of the systems platform group at STMicroelec- tronics, is well aware of the different definitions. Ghenassia is chairman of OSCI's TLM working group and the author of a recent textbook, Transaction-Level Modeling with SystemC.

"It's controversial," Ghenassia said. "At OSCI, [TLM] is really a way to write models in terms of function calls to exchange data. At ST, we have a more strict definition. For ST, it's more of an abstraction level with an associated model of computation."

That model of computation doesn't use cycles to synchronize concurrent processes; instead, it moves the synchronization up to a more abstract level. Synchronization might occur, for example, when a direct-memory access controller completes a data transfer and issues an interrupt.

Or, as Ghenassia noted in his book: "Components are modeled as modules with a set of concurrent processes that calculate and represent their behavior. These modules exchange communication in the form of transactions through an abstract channel." A transaction is defined as a data transfer or synchronization between two modules.