The server's building block is a palm-sized eight-way module, each holding four Power4 dice. Each Power4 chip includes two 64-bit, 1-GHz processor cores; 64-kbytes of instruction cache; 32-kbytes of data cache; and an L2 cache of 1.4-Mbytes, for a total of 174 million transistors.

IBM used a 0.18-micron copper process and silicon-on-insulator (SOI) substrates. By the second half of 2002, the Power4 design will be ported to a 0.13-micron process, which combines SOI, copper, and the SiLK low-k dielectric, improving die size, speed and power consumption.

Joel Tendler, director of technology assessment at IBM's server division, said a typically configured 32-way system will consume 8 kilowatts. Each die, with two processors running at 1.1 GHz, consumes about 115 W of power, which Tendler said was "quite efficient."

The Regatta servers, which also are called the IBM eServer p690 series, are air-cooled. Initial sales start at the high end, with eight-way, 16-way, and 32-way systems. Later, IBM will introduce the lower-end machines.

Each Power4 die delivers 808 SpECint2000 (integer) benchmarks and 1,169 SPECfp2000 (floating point) results.

About 250 members of the 300-person Power4 design team work in Austin; the rest are based in Rochester, Minn., and Poughkeepsie, N.Y.

The head of the IBM's Power4 design team, Mark Papermaster, expressed satisfaction that his project came in on schedule. Repeated delays in bringing out high-end processors have plagued IBM's rivals. Sun Microsystems' Sparc III, Hewlett-Packard's Superdome PA-RISC and Intel's Itanium were bedeviled by busted schedules.

"We delivered on time," Papermaster said, "with systems shipping in 2001, as we said we would. The train never got derailed. And we did it with an increase in performance. Originally we said we would hit a gigahertz, but we are shipping at a top frequency of 1.3 GHz."

Papermaster said that besides hewing to the schedule, the biggest challenge was dealing with timing and noise issues. "We used both vendor and proprietary design tools. Timing the design was a challenge, and at these high frequencies noise analysis required custom tools. We wrote thousands of lines of custom scripts for a vendor tool for the layout," he said.

IBM has 50 IBM fellows. Two worked on the Power4 project: Carl Anderson headed physical design and Ravi Arimilli led the memory-subsystem design team.

"We took a different path than our competitors with our decision to put two processors on each die. The interconnects, the chip-to-chip connections, operate at one-half the processor speed, or more than 600-MHz. That is much higher than any other company has accomplished, and Arimilli's team figured out how to do that," Papermaster said.

The Regatta servers also borrow techniques from IBM's mainframe group to partition the processors among finely grained tasks, getting more performance per dollar by an application on a single processor, if needed. Also, the servers include system architecture techniques to deal with any potential hardware failures, ensuring what Tendler called "application survivability."