Santa Cruz, Calif. -- EDA developers have pursued the dream of silicon compilation-- the pushbutton generation of IC layouts--for more than 20 years. Magma Design Automation this week will promise to make that dream a reality with Talus, a fully automated RTL-to-GDSII design suite that's said to be capable of implementing any IC, of any size, in two days or less.

"This is stage one of the silicon compiler dream," said Magma CEO Rajeev Madhavan. He said Talus can take a design from concept to completion with as few as three commands.

Slated for production deployment in September, Talus' code base differs from Magma's Blast Fusion, which will continue to address designs at 90 nanometers and above, as well as midlevel-complexity 65 nm, Madhavan said. Talus will target very complex chips with tens of millions of gates.

Talus provides an RTL-to-completion platform that concurrently analyzes and optimizes timing, area, power, signal integrity and yield. There are two versions. Talus LX will synthesize RTL netlists and will automatically generate physical partitions and power and clock prototypes. Talus PX will provide a complete physical implementation, including near-abutment layout, final physical partitioning, power and signal routing, and chip-level clock tree synthesis.

"If it works as advertised, this is the first of the DFM [design for manufacturing] generation of IC layout tools," said Gary Smith, chief EDA analyst at Gartner Dataquest. "That would make it one of the most significant EDA announcements so far this decade. But we need to get some customer feedback before we'll really know."

Talus is a departure from existing IC implementation tool sets, including Blast Fusion, Magma's flagship product, Madhavan said. Blast Fusion was originally targeted at block-level design. With the addition of floor planning, the tool tackled chip-level design.

But there's a problem with floor planning, Madhavan said: It is too reliant on the user's expertise. "Depending on who is piloting, the results will vary by a huge margin," he said. If automation is to become reality, floor planning has to be eliminated."

Further, said Madhavan, it takes too long to get through the RTL-to-GDSII implementation process, making it difficult to try what-if scenarios. "If you can do a chip in two days, the difference between a prototype and an implementation is very blurry," he noted.

Talus has many advantages over Blast Fusion, Madhavan said. They include multimode and multicorner analysis, integrated with crosstalk; full-chip-capacity RTL synthesis; support for distributed and multithreaded processing; full-chip-level clocking; and automated power strap layout. Talus uses an upgraded version of the data model used in Blast Fusion.

With the new tool set, manual floor planning is no longer needed, Madhavan said. Current EDA tools, he said, need manual floor planning because they don't view macros as cells, and because they have limited capacity and require manual power grid design. None of those limitations exists with Talus, he said. Users can still floor plan if they desire, however, and open application programming interfaces let users add their own algorithms.

Talus automatically creates and revises floor plans as RTL is modified. Using a technology called relative placement constraints, Talus can reproduce desired aspects of a previous floor plan. Relative placement takes into account the locations and constraints of neighboring cells, macros or pads. Users can "freeze" a portion of the design so that small changes don't have a big impact.

Concurrent multimode, multicorner analysis in Talus examines on-chip variation. What's new in Talus, Madhavan said, is that this is all done concurrently with crosstalk. Statistical timing will come with future releases.

Talus also adds routing algorithms developed in conjunction with IBM Corp. and Germany's University of Bonn. These include clocking algorithms for full-chip design. The main difference between Blast Fusion and Talus routing, Madhavan said, is that Blast Fusion uses a "window-based" routing approach, while Talus has a full-chip view.

Talus can start working when as little as 10 percent of the design's RTL is available, and it promises to create preliminary layouts, flat or hierarchical, within a few hours for any size design. Users thus can run a number of what-if analyses within a short period. Further, noted Madhavan, Talus will be tied to Magma's engineering-change-order capability, making it possible to push through a small change with minimal impact.

Distributed and multithreaded processing is what allows Magma to make the claim of producing final-quality layouts in two days. Magma has thus far run Talus on up to 16 CPUs, with a nearly linear increase in capacity, Madhavan said. Partitioning tasks to CPUs is automatic but can also be guided by the user.

Talus LX and PX are currently in limited release. Pricing information is not yet available.