Santa Cruz, Calif. — Taiwan Semiconductor Manufacturing Co. is about to make it easier for fabless chip designers working at 65 nanometers and below to get proprietary process data from the world's leading pure-play foundry. That could eliminate one of the biggest obstacles such developers face in sub-90-nm design and move them closer to an equal footing with designers at integrated device manufacturers, who can easily obtain process information from their own fabs.

TSMC this week will reveal a 65-nm design-for-manufacturability (DFM) "ecosystem" and a unified data format to bring process model information to EDA tools. Its 65-nm DFM-Compliant Design Support Ecosystem includes a rigorous qualification of third-party tools that support the foundry's new DFM Unified Format (DUF). So far, eight EDA vendors have qualified. The unified format, TSMC said, provides information needed for lithography process checks, critical-area analysis and chemical-mechanical polishing analysis. It will be available for 90- and 65-nm processes in July.

Difficulty in securing proprietary process data from foundries has been a stumbling block to fabless vendors' efforts in sub-90-nm design. Such data enables the model-based design-for-manufacturability that's becoming essential at 65 nm and below, where mere reliance on design rules is no longer sufficient to ensure good yields.

"This is an enormous step forward," said Ed Wan, senior director of design-services marketing at TSMC. "We are dealing not just with tools, but with an entire ecosystem. We set into motion an initiative that will weave DFM into every component of our design alliance partner program."

The initiative, he said, will serve TSMC's alliances with EDA vendors, library and intellectual-property providers, and independent design centers. "We're moving DFM capability to the designer's desktop, rather than what's been announced in the past, which is primarily the ability to run DFM functions at the foundry site."

Not surprisingly, fabless vendors greeted the news enthusiastically. Fabless chip maker Qualcomm, for example, was "very supportive" of the TSMC ecosystem effort, said Riko Radojcic, principal engineer responsible for design-to-silicon leadership at Qualcomm. "We will not have access to very intimate process data, but we expect to have access to the right data, as required to optimize the integration of process and design," he said. "In fact, we believe that with some of the new DFM technologies, we may be able to leapfrog the advantages that IDMs have traditionally had — by deploying a structured, model-based infrastructure, as opposed to the more informal and customized approaches that have typically evolved within IDMs."

Nitin Deo, vice president of marketing and business development at DFM startup Ponte Solutions Inc., calls the DFM Unified Format as big a step as the standardization of the Verilog language or the ".lib" format for libraries — two seminal events in EDA history. "It will take away the anxiety from the designers' minds, with the assurance that they have all the data they need to run the right tools," he said.

"This is a very important step forward for the industry as a whole," said Srinivas Raghvendra, senior director for DFM solutions at Synopsys Inc. "Customers who are already working at 65 nm are telling us that DRC [design rule check]-based signoff is not good enough anymore, and they want analysis tools to visualize how the layout will look in silicon."

"This is a huge breakthrough compared to where we were before," Joe Sawicki, vice president of Mentor Graphics' design to silicon division, said. "It enables designers to take control over their lives again."

No foundry can have as big an impact as TSMC, which last year held 44.7 percent of the total foundry market, including pure-play foundries and IDMs, a new report from Gartner Dataquest shows.

"TSMC was required to do this in order to keep the leading-edge ASSP guys happy, including Qualcomm, Freescale and Broadcom," said John Barber, research director at Gartner Dataquest. However, Barber noted, "it's really only going to target the top-tier customer base for TSMC."

Addressing DFM concerns
TSMC introduced a 65-nm reference flow last June, when it also rolled out Yield Plus, a set of process-related tool kits, and Yield Pro, a set of design services. TSMC quietly launched a "DFM-Compliant Initiative" that now includes 18 third-party companies.