The flows aim to speed time-to-manufacturing and reduce design uncertainty by focusing on design-for-manufacturing (DFM) issues such as timing and power variability prediction and optimization in the presence of process variations, according to the companies. The first flow, based on Extreme DA's Extreme XT sign-off tools, has been applied to a UMC test-chip at UMC's 90-nm process node, the companies said.

The partnership between UMC (Hsinchu, Taiwan) and Extreme DA (Palo Alto, Calif.) focuses on 65-nm design flow development, including design of test structures for collecting specific process variation data; extraction of pure random, spatially-correlated random, die-to-die random, and systematic variations in the front- and back-end processes; silicon verification of XT's statistical timing and extraction results. According to the partnering companies, using Extreme XT's statistical extraction and timing tools will allow mutual customers to utilize a variation-aware sign-off capability on UMC's proven 65-nm process.

Patrick Lin, UMC's chief SoC architect, told EE Times that UMC chose to partner with Extreme EDA on statistical timing and extraction after evaluating several EDA vendors of various size. "Extreme DA seems to be the most ready," Lin said.

Mustafa Celik, Extreme DA's CEO, said the company is currently in discussions with a number of fabless companies that are showing interest in statistical timing analysis, which requires process data from foundries.

"We thought it was a good opportunity to work with UMC to validate the approach," Celik said. "The next step is to go out and find potential customers."

Extreme DA, founded by former Artisan Components Chairman and EDA venture capital luminary Lucio Lanza, Celik and Carnegie Mellon University professor Larry Pileggi, emerged early last year to tout its statistical timing technology, which it bills as an enabler for 65- and 45-nm IC design. The company's main challengers in the space are heavyweight IBM Corp., which introduced its EinsTimer commercial tool just over one year ago, and big-time EDA vendors Magma Design Automation Inc., Cadence Design Systems Inc. and Synopsys Inc., each of which is said to have statistical timing analysis technology in various stages of development.

Instead of single numbers, statistical timing returns probability distributions, sensitivity graphs and yield curves, said to tell a designer how well a design will yield across a frequency range or predict worst-case performance across process variations.