There's been a lot of talk about the challenges of 65- and 45-nanometer IC design, and talk will turn into action next week at the 43rd Design Automation Conference in San Francisco. New and established vendors are fielding tools in such areas as design-for-manufacturability (DFM), statistical timing, IC physical verification, analog/mixed- signal design and electronic system-level design.

The 2006 DAC will include a large number of startups. Of roughly 250 exhibitors, 44 will be at DAC for the first time.

Everyone agrees on the need for DFM at 65 and 45 nm, but one key question is whether it should come from startups selling point tools or from the providers of IC physical-implementation suites. DAC show goers can expect that the three suppliers of integrated RTL-to-GDSII design systems--Cadence Design Systems Inc., Synopsys Inc. and Magma Design Automation Inc.--will all be talking about DFM capabilities.

Magma this week will tip a characterization-to-silicon DFM reference flow. It leverages both model- and rule-based approaches in order to predict lithography and chemical-mechanical polishing (CMP) effects (see story, page 34). "There are a number of companies coming out with point tools," said Kam Kittrell, general manager of Magma's design implementation business unit. "It's confusing for customers to create a DFM flow."

Sierra Design Automation Inc. will roll out Olympus-SoC, a netlist-to-GDSII system that supports "lithography aware" IC physical implementation. Sierra already offers physical synthesis and placement; Olympus-SoC adds detailed routing. Sierra doesn't offer RTL synthesis, but is clearly moving into a more competitive position with respect to Cadence, Synopsys and Magma. "All current place-and-route systems have architectures which are at least seven years old," said Sierra CTO Shankar Krishnamoorthy. "We believe that by starting from scratch, we can create a solution that offers the best in the marketplace."

Olympus-SoC is said to embed variation-aware timing, optimization and lithography modeling to address optical proxim- ity correction (OPC) effects early in the design cycle. Based on a high-capacity database, it includes a lithography-driven router that combines shape-based and gridded technologies. It also offers "live" interaction between route-based variability optimization and detailed routing. A timing analyzer supports CMP modeling.

Despite the existence of integrated IC implementation solutions, plenty of companies at this year's DAC will argue that DFM point tools are still needed. One big problem is where the necessary models come from. Startup Nanno Solutions Inc. earlier this month announced tools that generate accurate, worst-case interconnect models for delay, crosstalk and IR drop. CEO Darren Tay said that Nanno Solutions takes actual process variation data and turns it into realistic values for engineers. Nanno-Win generates statistically based interconnect models and Nanno-Cal generates netlists for floor planners, circuit simulators and delay estimators.

DFM provider Aprio Technologies Inc. last week introduced Halo-Quest, a tool that sits on top of EDA design and analysis tools to generate what the company calls a "DFM view." This includes the original layout, a version of the layout as printed in silicon and a series of error vectors that identify potential lithographic "hot spots."

Many tools analyze potential DFM problems, but only a few actually fix them. Sagantec Inc.'s DFM-Fix is a standalone tool that claims to remove lithography hot spots in IC layouts. The tool takes input from an initial post-OPC verification run.

Takumi Technology Corp. introduced itself in May with the mission of integrating complete DFM solutions. Last week it announced Takumi Inspect, a layout analysis tool that detects yield-impacting problems, and Takumi Enhance, an automated physical-design optimization system that can actually repair layouts to minimize hot spots.

Blaze DFM Inc. rolled out in April to address "electrical" DFM concerns around parametric yields. At DAC, Blaze will launch version 1.1 of its Blaze MO product, said to improve leakage and timing by optimizing and annotating design data for the OPC process.

One new technology that's widely anticipated is statistical timing analysis, which evaluates process parameters and returns statistical distributions rather than min-max timing numbers. Many think it will become important at 45 nm, and perhaps at 65 nm for performance-critical designs--but an infrastructure is needed first.

Startup Altos Design Automation Inc. will come to DAC with some technology that might fill the bill. Liberate is a library characterizer for traditional static timing analysis that claims to run 10 times faster than existing tools. But Altos will also be talking about Variety, which will evaluate process parameter variation and generate statistical libraries that account for random and systematic variation. CEO Jim McCanny said library characterization is running out of steam even for static timing analysis. Add in the demands of statistical analysis, he said, and it may take 20 to 100 times longer to build a library with existing tools.

Static timing analysis is still needed, however, and there's a new option from Incentia Design Systems Inc. Its TimeBench is billed as a complete timing analysis, management and debugging environment for 90-nm and 65-nm designs. It addresses on-chip variation analysis, signal integrity and constraint management.

Last month, market leader Synopsys announced NanoTime, its next-generation transistor-level static tool. Succeeding the earlier PathMill product, NanoTime adds a signal integrity capability and boasts a fivefold run-time improvement over its predecessor, said Bijan Kiani, vice president of marketing for the implementation group.

The analog wave
This year's DAC is seeing a burst of activity in analog/mixed-signal design. Startups Lynguent Inc. and Solido Design Automation Inc. are in the forefront. Solido has so far said little, but hinted that it has new technology in transistor-level design that will open a "new market."

But Lynguent announced its ModLyng product in late June. A modeling tool that incorporates a graphical user interface, ModLyng lets users build models from scratch by defining ports and parameters, drawing a model topology and writing equations. The tool generates models in Verilog-AMS, VHDL-AMS or the Analogy Mast language. "A graphical tool can introduce modeling to a new set of people who would not think of doing coding or programming," said CEO Martin Vlach.

Claiming to offer the first integrated solution for system-in-package (SiP) design, Cadence recently announced an RF SiP "methodology kit" along with several standalone tools for digital SiP design. Provided with consulting and a reference design, the kit includes SiP RF Architect, which hooks into the Virtuoso environment, and SiP RF Layout, which provides a package substrate layout environment.

Tackling IC physical verification, Mentor Graphics Corp. last week rolled out Calibre nmDRC, which promises fast run-times, dynamic debugging and integrated DFM capabilities. Calibre nmDRC is the underlying computational engine for the Calibre nm Platform, which includes design rule checking (DRC), layout vs. schematic, lithography-friendly design and extraction. "The previous standard for physical verification was overnight," said Joe Sawicki, vice president and general manager for Mentor's design-to-silicon division. "With this [Calibre nmDRC] tool, we get one-hour to two-hour run-times."

In functional verification, startup Liga Systems Inc. is introducing its first product this week (see story, page 34). The NitroSim plug-in "hybrid" simulator claims to boost RTL simulation by 10 to 100 times. NitroSim handles up to 300 million gates using a single PCI plug-in card with a custom VLIW processor. Once the netlist is compiled, everything runs like the user's original software simulation environment, said president and CEO Henry Verheyen. He called the $50,000 price tag "incredibly attractive" for customers used to expensive simulation accelerators.

Real Intent Inc. is announcing a breakthrough in formal verification with its Conquest offering, which provides automated verification at the "cluster" level. The tool, which claims to automatically construct proofs for multiple assertions, goes beyond today's block-level tools, said marketing vice president Rich Faris.

One way to deal with the increased gate counts at 65 and 45 nm is to move to a higher level of abstraction. Several vendors are attempting to do just that.

Startup CebaTech Inc. will announce plans to offer both TCP/IP intellectual property and the C-language electronic system-level (ESL) design tool that was used to create it. The company will offer a compiler that can compile C-language descriptions into synthesizable RTL code and compile untimed C into cycle-accurate C models (see story, page 36). This is not fully automated behavioral synthesis--the C code must be "structured by an architect to represent good hardware," said CTO Chad Spackman. But once done, the company said, an entire system-on-chip can be coded in C and run in a native C software environment with no need for RTL simulation.

Startup Javelin Design Automation Inc. is attempting to revive silicon virtual prototyping (SVP) with a tool that gives designers accurate physical information for making key decisions early in the design cycle. President and CEO Diana Raggett said that Javelin's "system physical prototyping" approach goes beyond first-generation SVP because it starts much earlier in the design process, can accept incomplete data and is more accurate. "We enable customers to see designs holistically, and to make intelligent trade-offs with a lot more information than they had before," Raggett said.