The companies applied dynamic voltage and frequency scaling techniques to an ARM926EJ-S test chip implemented in the TSMC 65LP process.

ARM (Cambridge, England) and TSMC (Hsinchu, Taiwan) claimed that the test chip achieved a dynamic power reduction of more than 50 percent compared with the same design in the same process without the benefit of dynamic voltage and frequency scaling. "We measured a dynamic power saving of just over 50 percent when scaling the ARM926EJ-S design from 1.2-V down to 0.8-V using our Intelligent Energy Manager implementation techniques," a spokeswoman said.

ARM and TSMC added that advanced power-gating technology reduced standby leakage by a factor of eight compared with the same circuit in the same process without the benefit of power gating and state retention.

ARM and TSMC are partnering on 65-nm and 45-nm technology development, and this project demonstrates the significant leakage and dynamic power reductions that we can achieve through close technical collaboration and implementation of fully functional silicon, said David Flynn, ARM Fellow, in a statement.

Power management features developed through the test chip program include multi-threshold voltage CMOS including dynamic voltage and frequency scaling (DVFS) to reduce dynamic and standby (leakage) power for different operating conditions.

ARMs Intelligent Energy Manager software already supports dynamic voltage and frequency scaling, and is now being extended to include leakage control using power gating and state retention under software control, the companies said.