This week's Design Automation Conference will make it clear that the EDA industry is counting on design-for-manufacturability (DFM) for a much-needed boost. But the restricted design rules (RDRs) that are quietly emerging for 45-nanometer and smaller geometries may reduce the need for some DFM tools and techniques, some observers say.

The RDR concept is surfacing from universities and IDM research labs and appears headed for a prominent role at 45 nm and below. The idea is to enhance manufacturability by restricting the layouts designers produce. For example, RDRs may set limitations on gate pitch and orientation, or even mandate that all gate-forming polysilicon features have the same orientation, width and pitch.

Depending on how restricted the RDRs are, the result could be regular structures reminiscent of gate arrays or programmable-logic arrays (PLAs). The compelling argument is that creating design layouts using only regular features will improve lithographic printability and make resolution enhancement technology easier to implement.

But very regular structures also carry potential area and performance penalties, causing some to argue that "extreme" RDRs, such as single-pitch, single-orientation rules, are unlikely to be adopted.

Most observers agree that some level of restriction seems inevitable. "All fabs are pursuing some form of RDRs at 45 nm," said John Lee, general manager of the physical-verification business unit at Magma Design Automation Inc. "Not all are equally restrictive, but all enforce regularity."

"What people are talking about is very regular structures, primarily in the active-device domains," said Ted Vucurevich, chief technology officer at Cadence Design Systems Inc. "This takes us back to the old days, in a sense, where you had gate array types of architectures and regularity of those structures."

RDRs have been proven out in a 45-nm design by IBM and are under advanced-stage development at other major chip makers, including Intel Corp., Advanced Micro Devices Inc. and Toshiba Corp., according to Gary Smith, chief EDA analyst at Gartner Dataquest. RDRs appear to be a shoo-in for at least some logic devices at 32 nm, according to Smith, who spoke on the topic at the Semicon West conference in San Francisco two weeks ago.

"It looks very promising," Smith said. "This is something that we are going to see a lot of." The use of RDRs will not make DFM tools obsolete, he said, but it definitely "limits the market for DFM."

'Dirty secret'
"RDRs are the dirty secret that DFM companies do not talk about, because strong RDRs may obviate the need for DFM," said Magma's Lee. The right solution, he said, is to augment RDRs with a physical-implementation system that includes lithography models, statistical timing and power, and correction and signoff with a physical-design tool.

Most observers see RDRs and DFM as largely complementary. That's the case at IBM, which has done much of the pioneering work in this area.

"RDRs do not eliminate the need for the model-based DFM techniques currently being discussed in the EDA industry," said Paul Farrar, vice president of process development at IBM's Semiconductor Research and Development Center. "When properly implemented, RDRs, in conjunction with model-based DFM, can simultaneously maintain design efficiency, schedule integrity and manufacturability. We have shown this on a leading-edge, high-performance 65-nm product."

As professor of computer science and engineering at the University of California at San Diego (UCSD), Andrew Kahng has published research on RDRs. And as CTO of DFM startup Blaze DFM Inc., Kahng does not believe that RDRs will make DFM unnecessary.

"Some aspects of DFM, such as closing the loop back from lithography simulation to device-level simulation, may become less critical," he said. "Other types of variability--reticle- and wafer-level biases, or misalignment distributions, for example--will remain a concern."

Kahng acknowledged that "extreme" RDRs, such as mandating only one pitch and orientation, would in fact "reduce the pressure" on DFM. But he believes such stringent measures aren't likely to take root, because of area and performance trade-offs. "DFM technology and tools should be kept in the picture with RDRs," he said. "They can dramatically reduce the degree of draconian rules you need."

Predictably, executives from major EDA vendors downplayed the potential for RDRs to wipe out the DFM market.

"While we see RDRs as a way to mitigate manufacturing issues, they are only one component, and they will certainly not lessen the need for a comprehensive DFM approach," said Srinivas Raghvendra, senior director of DFM solutions at Synopsys Inc.

"Some things are going to be easier [with RDRs], but I don't think people will dramatically change the tools and technologies they use to get chips out," said Cadence's Vucurevich.

He further cautioned that RDRs are not a done deal. "This is one approach, presuming that lithographic processes do not change significantly as we get down to 32 or 22 nm," he said. "If there's a change or improvement in the lithographic process, I don't see [RDRs] as a direction we'll necessarily take."