PORTLAND, Ore. — Research into competing architectures for the multicore processors of the future will take center stage this week when Intel Corp. demonstrates its Teraflop Research Chip—code-named Polaris—at the International Solid-State Circuits Conference in San Francisco.

The 80-core chip crunches 1 trillion floating-point operations/second when running at a 3.2-GHz clock speed and consumes 62 watts, to yield a record 16 Gflops/watt. And by cranking the clock up to 5.6 GHz, the chip bested 1.8 teraflops--that's 80 percent faster--albeit by increasing power consumption fourfold to 265 W, or 6.8 Gflops/W.

"Others are building massively parallel multicore chips, but with this research chip Intel is thinking outside the box," said Jim McGregor, who is principal analyst and research director of the Enabling Technologies Group at In-Stat. "Intel also plans to make the necessary software efforts to fully realize the capabilities of high-core-count chips, including special instructions, new software tool sets, new software development tools and new software compilers."

Last year, Advanced Micro Devices Inc. announced a coherent-processor approach to multiprocessors dubbed Torrenza and based on its proprietary HyperTransport CPU bus. Intel and IBM Corp. countered with Geneseo, a set of extensions to PCI Express that manages massively parallel computers using a content-addressable memory. Startups like Ambric Inc. (Beaverton, Ore.) have announced plans for noncoherent multiprocessor research chips. Ambric's Kestrel device will pack 360 RISC processor cores.

"Intel's 80-core chip is basically a mainframe-on-a-chip--literally," said McGregor. "It's the equivalent of 80 blade processors plugged into a high-speed backplane, or 80 separate computers using a high-speed hardware interconnect." The Teraflop Research Chip's hardware does the multitasking coordination "instead of depending on software, which just could not keep up with 80 cores," he said.

Photos reveal that almost a quarter of the area of each of the 80 cores is dedicated to the mesh router, which can simultaneously coordinate communication among any adjacent cores. Also on board is a 3-D vertical path to static random-access memory that will be located on a planned separate chip stacked above the processor chip.

"AMD took the first step by integrating a crossbar switch into each core on their X86-based multiprocessor, but Intel's effort goes beyond having just one switch per core," said McGregor. "Intel's router-per-core will aid in performance scaling and power scaling as well as enabling self-repair of chips, since if one of the cores gets damaged they can just disable it and route around it in a manner transparent to software."

All these chips are aimed at massively parallel applications enabling higher-performance computing abilities for scientific simulations, such as for global-warming and weather mapping; data-intensive applications where massive amounts of information have to be processed, such as financial modeling and transaction processing; and security applications, where massive databases need to be scanned in real-time.

"All these multicore processors will initially be aimed mainly at enterprise-level applications, though there are also possibilities for consumer applications in the future, such as creating virtual environments," said McGregor. "As time goes by, more and more applications will be able to use these massively parallel capabilities." He cited, for example, medical applications, "where you have to compare tons and tons of images and view them anywhere in the world."

Made in Ireland

Intel fabricated its 80-core Teraflop Research Chip in its Ireland manufacturing facility, using a state-of-the-art 65-nanometer process. Each core houses two single-cycle floating-point units, which were first described in another ISSCC paper presented two years ago. The 80 cores are arranged in a 10 x 8 two-dimensional mesh network, with each core housing a router with five I/Os--four of its paths going to adjacent processors and one going out vertically to an SRAM chip stacked 3-D style above them.