San Jose, Calif. — The arcane realm of electrostatic discharge will finally reach the limelight--and perhaps the boiling point--this month as a group of leading chip makers pushes to reduce the specifications for ESD in digital ICs. But some detractors suggest that lowering ESD levels is reckless, and could lead to catastrophic quality and reliability problems for semiconductors.

The Industry Council on ESD Target Levels is expected to hammer out a white paper at the International Electrostatic Discharge Workshop, which convenes May 14-17 in Lake Tahoe, Calif., in support of a proposal to reduce on-chip ESD stress target levels by more than half. The reduction is supposed to lower cycle times and costs for chip makers, which are struggling to meet the current ESD levels in new designs. According to the council, those levels are outdated and represent "overkill," causing unnecessary debugging time, IC respins and product delays. The group maintains that its proposal will not compromise quality or performance.

The council, which hopes to muster industry consensus around its plan by 2008, will present its white paper to the Jedec standards body. Jedec is not expected to recognize the proposal as a formal standard, but may endorse or "classify" the new ESD target levels.

As both chips and systems become smaller and more complex, product failures increase in tandem with the levels of electrostatic discharge. The cost for ESD-damaged devices ranges from a few cents for a simple diode to several hundred dollars for complex hybrids, according to the Electrostatic Discharge Association, a group based in Rome, N.Y.

Besides devising new target levels, the Industry Council on ESD Target Levels is also attempting to gain acceptance

for the proposed ESD levels among their respective customers. The council, which was formed last year, consists of 16 major companies: Analog Devices, Advanced Micro De- vices, Freescale, Fujitsu, IBM, Infineon, Intel, LSI, Matsushita, NXP, Oki, Renesas, Samsung, Sarnoff, Texas Instruments and TSMC.

But given the fact that OEMs are under pressure to boost the ESD protection levels in their products, system makers are reportedly unhappy with the efforts to lower the standards. Lowering the ESD levels "is kind of a joke," said one vendor. "What you're doing is giving up reliability. In other words, the semiconductor community is passing the buck and making ESD someone else's problem."

Even one ESD council member contends that reduced ESD levels spell potential trouble for the electronics industry. "I don't think it's a good idea," said Koen Verhaege, executive director of Sarnoff Europe, part of Sarnoff Corp. (Princeton, N.J.). "Changing the standard specifications today, without proper data and without decisive and objective proof that indeed quality and yield will not suffer, is reckless and could be lethal to divisions, to companies and to businesses."

Sarnoff is a supplier of intellectual property for ESD protection, and some contend that the company's opposition may be tied to its IP business, which could be threatened if the ESD target levels are lowered. "They do not make ICs, so their motives may be different than ours," said Charvaka Duvvury, a fellow in Texas Instruments Inc.'s Silicon Technology Group and one of the industry's foremost experts on ESD.

Duvvury claimed that current ESD target levels are "overkill" for today's IC designs. He insisted that the lower on-chip ESD target levels the council is proposing will not affect chip quality, reliability or performance. In extensive field tests conducted by the ESD council, digital chips with reduced ESD levels had relatively few problems or field returns, he said.

The only challenge now is convincing the customers. "Naturally, there will be a pushback," Duvvury said. "One of the concerns among customers is that we're doing this for our own benefit."