A handful of vendors showed prototype chips for Express version 2.0 that doubles transfer rates, including Intel Corp. which promised to ship before the end of the year its first chip set supporting the spec. In addition, PCI SIG members provided more detail on some of the early work toward scoping out a follow-on generation architecture for products that could hit in late 2009.

Separately, at least one vendor demonstrated a working version of PCI Express cabling to expand server I/O within or beyond a single chassis. The group also reported progress on specs for high-end graphics and for I/O virtualization in servers.

The big focus for the conference was the move to Express 2.0. ARM, LSI, NEC and Synopsys showed basic demos of typically physical layer blocks handling up to the 5G transfers/second of the spec, some of them using existing 6.25 Gbit/second serdes.

Intel demonstrated unreleased AMD and NVidia graphics chips riding its Stoakley chip set for workstations which offers two Express 2.0 ports supporting 16 parallel lanes each. The chip set will also see early use in technical computing systems, said David Fair, an I/O specialist in Intel's server group.

Graphics are seen as the major driver for the next generation of Express. However, next generation 10 Gbit/second networking cards will also use Express 2.0, said Harmel Sangha of LSI.

The PCI SIG is refining its compliance tests for Express 2.0, promising to have them complete before a plugfest scheduled for early December in the San Jose area. Vendors hope to ship production versions of compliant products after that meeting.

To get the faster data transfers, Express 2.0 cut allowed jitter in half and tightened impedance to 85 Ohms from 100 Ohms in the version 1.1 spec that offers 2.5 G Transfers/second. Single connector lengths were also shortened from 12 down to 6-8 inches in some cases and two connector implementations will require stripline rather than microstrip traces. The new spec also requires some adaptive transmitter de-emphasis.