The first silicon has four XCore 32-bit processor tiles, each able to share up to 500MIPS of performance across up to 8 threads and Noel Hurley, vice president of customer marketing, demonstrated a game of 'Pong' written as software and implemented on the XCore development platform, to journalists at a meeting here. XMOS uses the phrase "software-defined silicon" to describe its product.

However, Hurley declined to be drawn on the numbers of XCore tiles that would be included on the products in the XS-1 family. Engineering samples are due to be available to selected customers from Jan.1, 2008 with volume production beginning in the middle of the second quarter of 2008 according to XMOS documentation.

In essence the XMOS architecture is similar to a field-programmable gate array but with the look-up-tables replaced with multithreaded event-driven processors that can work closely with I/O pins and data streams. Control is effected by an embedded software design flow that uses C/C++ compilers and XC a special-purpose language with timing features added to C. By using C-based behavioural languages, designers can quickly map white-board functional specifications into silicon, according to XMOS.

Test chips were produced by Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) on its 90-nm general purpose process.

"We estimate that the worlds universities are producing 20-30 software designers for every hardware engineer. This shouldnt be a surprise, since the responsibility of product differentiation increasingly lies in the software domain," said David May, CTO and founder of XMOS, in a statement. "By introducing an accessible and familiar processor architecture, tightly coupled with an event-driven system and multi-threading philosophy we are offering todays silicon designers with the tools they really need."

The XCore processor is tightly coupled to the outside world through a set of event driven input-output ports, and inter-thread communication is provided by XLink", a channel mechanism that allows threads and XCores to interact at the hardware level. These bridges between the physical world and the processor engine provide a stable and simple interface for the software designer and the hardware engineer.

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