The partners include AMD, Chartered Semiconductor Manufacturing, Freescale, Infineon, Samsung and IBM.

Using high-k/metal gate process technology, IBM and its partners have been able to shrink the size of a chip by up to 50 percent as compared with the 45-nm devices, which are not yet in volume production. The 45nm devices are expected to start ramping at the end of first quarter 2008.

IBM said that high-k metal gate chips save about 45 percent total power and offer up to 30 percent higher performance, as documented in measurements performed at IBM's East Fishkill, N.Y., semiconductor-manufacturing facility.

The alliance partners have developed and demonstrated a 32nm SRAM with cell sizes below 0.15um2.

They have also incorporated high-k silicon-on-insulator (SOI) technology at 32nm for high-performance applications. The high-k material properties enable a 30 percent transistor speed increase over the previous generation of high performance SOI technology.

"This industry-leading development comes from leveraging the collective engineering talent across the six partner companies, as well as world-class R&D facilities, such as the Albany Nanotech Research Center, in order to maintain an aggressive road map," said Gary Patton, vice president, IBM's Semiconductor Research and Development Center.

Separately, Intel has made 32nm announcements, but Patton believes "IBM is first in developing working SRAMs in 32nm for both low-power and high-performance applications."

The IBM alliance achievements come at a time when market analyst firm Gartner predicts that, for chip makers, process-development costs for 32 nm could hit $3 billion, twice the level of 65nm process technologies. Costs for a 32nm fab are estimated to reach $3.5 billion.