The $7.5 million, three-year program, which is funded jointly by SRC and New York State, begins this month, with the UAlbany NanoCollege serving as home for the New York Center for Advanced Interconnect Science and Technology (NY CAIST) program.

As well as the College of Nanoscale Science and Engineering (CNSE) within the University of Albany, other academic institutions participating in the project include Columbia University, Cornell University, Lehigh University, Massachusetts Institute of Technology (MIT), Penn State, Rensselaer Polytechnic Institute (RPI), Stanford, SUNY Binghamton, University of Florida, University of Maryland, University of North Texas, University of Texas at Arlington and the University of Texas at Austin.

As part of the NY CAIST program, 27 research projects are planned, aimed at extending copper and low-k dielectric scaling that will ultimately serve chipmakers.

"Since interconnect performance is starting to dominate chip performance more than devices do, interconnect research is increasingly important to ensure continued scaling of semiconductors," said Scott List, an Intel assignee who is director of interconnect and packaging research at Global Research Collaboration (GRC), a unit of the SRC that is responsible for narrowing the options for carrying CMOS to its ultimate limit.

"Interconnect scaling is fully half the solution for technology required to drive chip geometries beyond 22 nanometers. As we evaluate options like carbon nanotubes and optical interconnects, we have found there are few viable interconnect choices for implementation at 22-nm. It is vital that we continue to build upon the progress weve made with NY CAIST toward copper and low-k scaling," added List.

The researchers note that, year-on-year, switching speeds on chips have grown nearly 20 percent faster with a 30 percent wire and transistor density increase. However, the ability to continue this pace will eventually slow down without implementation of new interconnect materials, processes, metrology and concepts.

The SRC and NY CAIST at CNSE will co-ordinate under one roof cross-functional collaboration of researchers in areas such as : Reduction of the sidewall and grain boundary scattering to decrease copper resistivity at sub-40nm dimensions; development of a new class of Cu diffusion barriers with thicknesses of a few atoms, development of metrology to measure buried interfaces with atomic resolution, optimization of the size and structure of voids in low-k dielectrics on the scale of a few atoms to increase speed while maintaining strength, and understanding the fundamental failure mechanisms in interconnects to reduce shorts in the dielectrics and opens in the Cu wires.

The research will build on and enhance work conducted at NY CAIST over the past three years by SRC, GRC and its academic partners.

Previous results include the demonstration of 50 percent reduction in the sidewall scattering from the edges of the Cu wires, sub-ten-atom thick diffusion barriers and evaluation of novel optical and carbon nanotube-based interconnects.

The International Technology Roadmap for Semiconductors (ITRS) expects the 22-nm node to be implemented in commercial production by 2011-12.

Last September, in a related effort, the SRC and the Commerce Department's National Institute of Standards and Technology (NIST) announced a partnership to support research in nanoelectronics.

The plan is to demonstrate the feasibility of next-generation circuits over the next 5-to-10 years.

Over the next year, NIST will contribute $2.76 million to the effort, which when combined with funds from industry, will provide close to $4 million of new research grants.