The so-called Berkeley Emulation Engine version 3 (BEE3) aims to help researchers quickly prototype processors with hundreds or thousands of cores and try out new ways of programming them. Launched as a project by the University of California at Berkeley, the latest version was designed as a commercially available system with significant help from Microsoft Research.

"What I am hoping is things like BEE3 will revitalize research in computer architecture," said Charles Thacker, a computer pioneer and technical fellow leading a small systems architecture team at Microsoft Research.

The system is the centerpiece of the Research Accelerator for Multiple Processors (RAMP) program between Berkeley, Microsoft, Intel and five other major US universities including MIT and Stanford. The effort is part of a broad search for new ways to build computers now that chip designers have determined they can no longer push raw data rates due to power leakage.

"I was in computer science research for 25 years and found the work got to be pretty boring because it became very incremental, with a lot of papers reporting on five percent performance increases," said Thacker who led the team at Xerox PARC that developed an early prototype for the personal computer.

"That's not how it was 30 years ago when the field was wide open and it was easy to do seminal work," Thacker said. "Today if you want to do something competitive with Intel you have to spend an incredible amount of money, but now with FPGAs you can simulate what you want. It doesn't run as fast [as an Intel processor], but it runs fast enough," he added.

Several universities built early versions of the BEE system for their own internal use. The latest version was design with help from Microsoft and contract manufacturer Celestica, aimed at creating a general purpose industrial computer for researchers.

Celestica is currently doing a final re-spin of the main printed circuit board, and Berkeley researchers are wrapping up work on a peripheral control board. The design is being made available on a royalty-free basis.

"Fundamentally FPGAs are now large enough and the tool suites good enough that a small number of people can build a fairly substantial system," said Thacker. "At the Berkeley wireless lab they have already built a thousand-processor machine with an array of these systems racked up," he said.

The latest version uses four Xilinx Virtex 5 LX110T FPGAs and up to 64 Gbytes main memory. It has eight 10 Gbit/s CX4 Ethernet ports and four PCI Express slots.

"It could be useful across a wide range of apps given its flexibility and the substantial pile of RAM on the board," said Thacker who describes BEE3 as a Swiss Army knife of computer research tools.

Thacker would not say what parallel programming approaches Microsoft expects to try out on the system other than jobs related to its published work on atomic transactions. "Many of our efforts will not be public for awhile and they are still very speculative," he said.

Asked what approaches he thinks are most promising Thacker said "I don't have a real good idea yet, I'm afraid. It's hard to predict the outline of the research or state milestones, but we will try many tings and collaborate with universities," he added.

In addition to the BEE3 work, Microsoft has been bolstering its ranks with supercomputing experts such as Burton Smith and Dan Reed. In addition, Microsoft and Intel teamed up to fund a new parallel computing lab at Berkeley expected to be announced soon.

Top computer science researchers have said the industry is at risk of hitting a wall if it cannot deliver a useful parallel programming model for next-generation multicore chips son. Thacker had no comment on whether the industry as a whole is doing enough to tackle what is seen as an enormously difficult problem looming on the horizon.

"I don't know about the industry as a while but I think we do pretty well," he said, pointing to the work on the BEE3 design. "It is a lot of work and we spent quite a bit of money on it," he said.