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GDDR5 enters picture for next-gen graphics
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A high-speed memory interface is emerging to feed the next-generation graphics controllers expected to ship as early as June from Advanced Micro Devices and rival Nvidia Corp. Parts are expected initially to deliver a whopping 4 Gbits/second per pin, scaling to as much as 7 Gbits/s per pin.

The full impact of the Graphics Double Data Rate, version 5 (GDDR5) interconnect, defined by Jedec, is still unclear at a time when the graphics chips--including a new architecture from Intel Corp.--remain under a cloak of secrecy. But excitement is building as players plow a path to new levels of performance.

Hynix, Qimonda and Samsung are already shipping memory chips using GDDR5. The spec, which could be officially published in September, adds features to cut power and cost while increasing bandwidth over today's mainstream GDDR3 interface.

Joe Macri, senior director of circuit engineering for AMD's graphics group, said he expects AMD, Nvidia and Intel to use the interface on their next-generation graphics controllers. The interface will also be a good choice for next-generation videogame consoles, said Macri, who chairs Jedec's DRAM committee as well as the task group that defined GDDR5.

"We would not have three vendors bringing DRAM products to market in such a short space of time if only one graphics vendor was going to support it," he said, citing a May 21 press release in which AMD vowed to use GDDR5 for its next Radeon graphics chips. "Intel, Nvidia and others were all there defining [GDDR5] and, I suspect, will design with it."

The question is when. Barry Wagner, a director of technical marketing for Nvidia and vice chairman of the GDDR5 group, would not comment on Nvidia's next-gen controllers. But he downplayed the memory interconnect's significance. "Memory bandwidth is not really a predictor of success or performance. It's a second- or third-order effect on performance, which is primarily influenced by the controller architecture," Wagner said.

For its previous-generation controller, the GeForce 8800, Nvidia used a 384-bit GDDR3 interconnect that it later scaled down to a 256-bit-wide version. The part competed against an AMD R600 using a 512-bit GDDR4 interconnect. Both links were clocked at about 1 GHz, but the Nvidia part was widely seen as having superior performance. "With less memory bandwidth, we had a sufficiently better product," Wagner claimed.

For next-generation parts, Nvidia could continue using GDDR3, now sampling at 1.3-GHz frequencies. "It's not completely out of gas," Wagner said. DDR3 system memories in x16 and x32 widths could become options if they hit low enough price points, he added.


Click here for larger image

Clearly, AMD does not want to see a repeat of the GDDR4 experience, when only AMD and two DRAM makers supported the spec. "The ecosystem never fully developed," said Macri. "It achieved its technical goals, but it never did as well in the market as it could have."

Macri said Nvidia helped define GDDR4 but decided not to use it, because the spec used 8 bits minimum for certain burst operations. Nvidia's graphics chip at the time was designed for a more traditional, 4-bit burst.

Just what the next-generation controllers will offer and when they will ship is still unclear. Thus, it's also unclear what mix of memory interfaces AMD and Nvidia will use. Overall, the former ATI graphics group is regaining some momentum and market share after having fallen behind during the period of its acquisition by AMD. Today, Nvidia commands about two-thirds of the market for discrete graphics chips; AMD takes the other third.

"It looks like the the graphics group at AMD has been making up time, and we are getting back to more of a horse race," said Dean McCarron, principal of market watcher Mercury Research (Cave Creek, Ariz.).

Typically, the companies release a new controller every 12 to 18 months, with a process shrink as a midlife kicker between generations. "It's an insane pace," McCarron said.



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Related Links:

  • Qimonda white paper on GDDR
  • The EE Times blog on interconnects



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