PORTLAND, Ore. — Interconnecting bare die to form 3-D chip stacks is best done by low-temperature wafer bonding before dicing, according to Rensselaer Polytechnic Institute (RPI) researchers who described how to perform the process with nanoscale copper rods.

Using a chemical vapor deposition technique, the researchers were able to demonstrate how "intermittent annealing" provided lower temperatures to melt the copper nanorods, enabling safe bonding of wafers into a single stack that could then be diced into 3-D chips.

The process offers a "low-temperature option for bonding silicon wafers together when assembling 3-D chips," said Pei-I Wang, research associate at RPI's Center for Integrated Electronics. "Less heat is needed to anneal the slimmer nanorods; we've seen them anneal as low as 300 degrees Celsius."

Dicing after wafer bonding, rather than before bonding, provides better alignment since wafer handling tools are more precise than chip-handling tools. However, a low-temperature bonding method is needed to avoid damaging circuitry already on wafers.

The RPI demonstration of nanorod-enabled wafer bonding is the first to be accomplished at the relatively low temperature of 300 degrees C. Diffusion annealing, for instance, is usually performed at temperatures as high as 650 degrees C. RPI's 300-degree C annealing process is too low to affect chip performance, potentially raising yields for future 3-D chip stacks.

The researchers have applied for a patent on the process of using intermittent interruptions in the deposition of copper nanorods. During the interruptions, nanorods are briefly exposed to oxygen, which makes them grow straighter and thinner. The resulting copper nanorods studding interconnection vias were as small as 10 nanometers in diameter, compared to more than 100 nanometers for nanorods grown without interruptions.

Funding for RPI's research was provided by the New York State Foundation for Science, Technology and Innovation and the Interconnect Focus Center-New York.