The biggest surprise is silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), which isn't supposed to have its high-k/metal-gate solution ready until the 28-nm node.

IBM's ''fab club'' has recently disclosed the details of its 32-nm process with high-k and metal gates. This week, the group will present a paper on a 32-nm FinFET with a high-k/metal-gate scheme.

Also at IEDM, the NEC/Toshiba duo will present a ''cost-conscious'' high-k/metal-gate scheme. Last week, Intel Corp. rolled out its 32-nm process, based on a second-generation, high-k/metal-gate scheme.

There are two basic approaches to the next-generation gate stack in logic designs. IBM's ''fab club'' is using a gate-first approach to the high-k/metal-gate scheme, while Intel is deploying a rival replacement-gate technology. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.

At IEDM, TSMC will present a paper about a 32-nm process, which includes a high-k/metal-gate scheme based on a gate-first technology. A 0.15-micron² SRAM cell was developed by using a hafnium-based material and 193-nm immersion lithography with a numerical aperture of 1.35, according to TSMC's paper.

TSMC's high-k material has been scaled to 10 angstroms. ''Drive currents of 1340/940-uA/um are achieved at I_off=nA/um, V_dd=1V, 30-nm physical gate length and 130-nm gate pitch,'' according to the paper.

It's unclear if TSMC will offer the technology at 32-nm, however. The company said it plans to roll out high-k at 28-nm, which TSMC considers as its ''full-node'' technology.

In a separate paper, the team of NEC Corp. and Toshiba Corp. disclosed that it has developed a 32-nm process, with a single-exposure lithography technology and a ''gate-first'' high-k/metal-gate process. The chip makers have demonstrated a SRAM cell of 0.124-micron² and a gate density of 3650 kGate/mm², according to the paper.

At various times, IBM and its technology partners have talked about their 32-nm process with high-k and metal gates. IBM's partners include AMD, Chartered, Freescale, Infineon, Samsung, ST and Toshiba.

Moving beyond the planar transistor, IBM, AMD, Freescale and Toshiba will present a FinFET with high-k and metal gates for the 32-nm node and beyond. An SRAM cell was devised at areas down to 0.128-micron², which is said to be the world's smallest FinFET cell to date, according to the paper.

Using 22-nm design rules, the cell was fabricated using a CMOS process flow and e-beam lithography. The cell was also devised using ''off-center design contacts and L-shaped bars,'' according to the paper.

In the cell, fin pitch was 80-nm, gate pitch and L_g were 110-nm and 30-nm. To enable high-k and metal gates, CVD-based HfO₂, PVD TiN and polysilicon were deposited on the Fin portion of the device.