Rambus claims the prototype shows the technology from its main memory initiative announced in May can provide a 50 percent improvement in data throughput while lowering power consumption by 20 percent compared to today's dual in-line memory modules (DIMMs).

"Our innovative module threading technology employs parallelism to deliver the higher memory bandwidth needed for multi-core systems while reducing overall power consumption," said Craig Hampel, a Rambus fellow who will describe the prototype at IDF.

The demo marks a proof point in Rambus' efforts to get companies to adopt the technology as the industry considers what lies beyond today's DDR3 standard. So far, no chip sets support the Rambus approach.

"We're still in the evangelism stage," said Michael Ching, a director of marketing at Rambus. "We've been told the problems we are trying to solve are the right ones," he said.

The rise of multicore processors is increasing the need for more memory bandwidth in power-constrained systems. Rambus is addressing the issue by effectively splitting a DIMM into two independent resources that can be accessed in parallel.

By accessing only half the device's memory chips at a time, the approach cuts activation power in half, Ching said. By dual threading memory accesses, the device has fewer wait states and CPUs can queue more transactions in parallel, increasing throughput, he added.

The Rambus approach requires module makers to add new traces to their boards to create the separate left and right DIMM channels. Memory controllers need to add hardware to implement the threading technique.

Rambus is embroiled in multiple court cases regarding its patents on existing memory technology, some stemming from allegations it withheld knowledge of its patents in industry standards meetings. The company no longer participates in standards meetings related to future memory technology.