Intel has an edge in 32nm with the Westmere family it will describe at ISSCC. Dual-core versions of the architecture, essentially a shrink of Intel's existing Nehalem design, are already shipping. Six-core server versions are expected to hit the market before June, said Nathan Brookwood, principal of Insight64 (Saratoga, Calif.)

Intel's six-core Westmere—to be described in one ISSCC paper--packs 1.17 billion transistors, uses a 12 MByte shared L3 cache and supports low-voltage DDR3 memory. The paper will also describe a new anti-resonance feature of Intel's QuickPath Interconnect that lowers jitter.

AMD will compete in 2010 with a host of 45nm processors including Magny Cours which will pack two six-cores dice in a single 12-core package for PC servers. For its ISSCC paper, AMD will leap ahead to its 2011 road map to describe a 32nm core capable of data rates above 3 GHz and power consumption variable from 2.5 to 25W.

Just which core AMD's paper describes is not clear. The company's 32nm designs shipping in 2011 include two new cores and some existing ones moved to a 32nm process.

Much of AMD's paper will focus on circuit techniques the company is using to lower power consumption and leakage of the core. For example, the core's L1 cache uses 8T memory cells to support low supply voltages. The chip also uses a power gating ring that takes advantage of isolated substrates used in the company's silicon-on-insulator technology to provide a near-zero power off state.

Separately, Intel will present papers describing research on three different kinds of on-chip networks it could use in future multicore chips.

One research device built in 45nm technology uses 48 x86 cores on a 6x4 mesh network. It uses a message passing scheme with on-chip shared memory to implement a virtual cut-through network with 256 Gbytes/second bisection bandwidth.

A separate paper will describe an experimental circuit-switched streaming network protocol applied to a 64-node on-chip mesh network, supporting aggregate network throughput of 2.6 Tbits/s. A third research paper will describe a ring interconnect bus that delivers 1.2 Tbytes/s bandwidth among eight on-chip Xeon cores.

Separately, IBM will present two papers on 45nm implementations of its Power architecture using embedded DRAM. One part uses eight Power7 cores based on the company's latest architecture described in August at the Hot Chips conference. The other uses 16 cores of an unspecified Power generation along with a set of security and network accelerators.

For its part, Sun Microsystems will describe its Rainbow Falls chip that uses 16 cores supporting eight threads each in a 40nm design. The CPU was initially described at Hot Chips.