EETimes.com - Intel provides peek of next-generation Pentium

EE Times: Semi News

Intel provides peek of next-generation Pentium

Rick Merritt
EE Times
(02/19/2003 12:33 PM EST)

SAN JOSE, Calif. — Intel Corp. engineers gave a sneak peek at Prescott, the company's next-generation Pentium 4 processor, at the Intel Developer Forum here Wednesday (Feb 19). Intel said the 90-nm processor due for release late this year will sport process and design improvements that will help Intel crank the Pentium up to a 5-GHz frequency.

"With Prescott, we will be the first company in production with strained silicon and this will give us a clock-rate advantage," said Joseph Schutz, a director of microprocessor design at Intel.

Perhaps the biggest achievement of the Prescott design team was in reducing clock skew across the die by adopting a new clock distribution scheme. While not detailing how that scheme works, Schutz said it would nearly eliminate RC coupling that resulted in the 20-picosecond skew found in the previous-generation Northwood CPU.

"We developed a new approach for clock distribution on Prescott that averages the skew out. The approach is scalable to different die sizes. You'll see this approach used on a number of Intel products in the future," Schutz said.

Prescott is also Intel's first processor to support a security technology code-named Le Grande. While Intel has not yet detailed the technology, it is believed to provide a protected space in main memory for a secure execution mode required as part of Palladium, a new PC security scheme being developed by Microsoft Corp.

Prescott adds 13 new instructions to the Pentium instruction set, including one for video encoding and two for thread synchronization to enhance Intel's approach to simultaneous multithreading, which Intel calls Hyperthreading. Like Northwood, the Prescott processor will support two simultaneous threads.

Other new instructions support complex arithmetic operations, floating-point-to-integer conversions and SIMD floating-point operations.

Prescott supports improved pre-fetch branch predictions. The CPU also adopts a new approach to chip layout based on placing individual cells in locations aimed at enabling the fastest clock rate for the processor.

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