United Business Media EE Times


Search

HOMELATEST NEWSSEMICONDUCTORSMOST POPULARMARKET INTELLIGENCE UNITFORUMSDESIGNNEW PRODUCTSCAREERSBLOGSCONTACTEVENTSSIGN UP!RSS

 

EUV activity shifts to Sematech North








EE Times


AUSTIN, Texas — Developers of extreme-ultraviolet (EUV) lithography are looking north, specifically to the University at Albany, State University of New York, for their future. Next week, the first of two planned 300-mm clean rooms will open at the University at Albany's Nanoelectronics Center, with International Sematech North as the anchor tenant.

Success at Albany is essential "if Moore's Law is to continue past 2010, when optical lithography — probably 157-nanometer scanners with immersion enhancements — almost surely will run out of steam," said Kevin Kemp, EUV program manager at International Sematech, here.

The Albany center also will be home to a separate IBM mask development effort, expected to be detailed soon by IBM technologists. Tokyo Electron Ltd. (TEL) has committed to a $300 million R&D center at Albany, taking advantage of liberal funding support from the state of New York.

The various EUV programs at Albany are being established as the EUV LLC, a consortium of semiconductor manufacturers supporting the development of an EUV scanner, winds down its work in Livermore, Calif. The shift north also comes as many of the scientists from the Berkeley, Livermore and Sandia national labs who have been working on EUV-related projects at the Virtual National Laboratory in Livermore are moving on to different national-security projects.

While ASML, Nikon Corp. and Canon Inc. pick up on the EUV scanner work begun at Livermore, Albany will serve as the center for mask blanks and photoresist development, two critical parts of the EUV infrastructure.

Defect-free zones

Mask blanks are reflective elements in the optical path, which means their coated surfaces must be free of any printable defects. Figuring out how to ensure a defect-free surface is just one of the challenges developers at Albany face.

Shortly after the first 16,000-square-foot clean room opens at Albany, Sematech North will install an ion beam deposition tool from Veeco Instruments Inc. (Woodbury, N.Y.) that will drop the 40 to 50 pairs of molybdenum-silicon layers needed to form the reflective coating on the square mask blanks. The circuit patterns will then be deposited normally on the blank's surface, said Kurt Kimmel, an IBM assignee to Sematech and the mask program manager.

By July, the Albany center will have metrology and cleaning equipment operating, and work will be fully under way to reduce the number of defects on the mask blanks.

The second focus of the Sematech North effort, EUV resists, will be housed in the second clean room at Albany Nanotech, now under construction. Sematech North will create EUV test patterns by putting an EUV exposure tool from Exitech Ltd. (Oxford, England) in place by the end of the year. The Exitech system includes technology licensed from the EUV LLC.

The Exitech microstepper has a tiny field size, of about 1 square millimeter, but a respectable depth of field from the 0.3-numerical-aperture (NA) Zeiss optics. Kemp said the tool will support resist development for 30-nm lines and spaces, a change from the 70-nm patterns on the EUV engineering test stand EUV LLC developed. That first-generation EUV scanner had an initial set of 0.1-NA reflective optics that delivered a standard field size of 25 x 31 mm, but with limited depth of field.

Creating a resist for such small features requires finding the optimum trade-off between line-edge roughness and sensitivity, or how many photons it takes to expose the pattern, which translates into throughput on the factory floor.

"It's relatively easy to make a resist that is sensitive to the EUV wavelength 13.5 nm. But there is an almost inherent trade-off between the line-edge roughness and good sensitivity," Kemp said.

The EUV resist center at Albany will work with commercial resist suppliers, much as Sematech is doing in Austin now while developing a resist for 157-nm lithography. One of the leading resist suppliers, Shipley Co., a subsidiary of Rohm and Haas Co., recently opened its $30 million Advanced Technology Center in Marlborough, Mass., to develop next-generation resists, low-k dielectrics and other materials.

Reducing the number of printable defects on the mask blanks will require a concentrated effort from the EUV Association in Japan and the EUV projects funded by Medea Plus in Europe, in addition to Sematech North, Kemp said.

"Creating truly defect-free blanks is extremely difficult," IBM's Kimmel said. The mask-creation industry lags behind the wafer-processing sector in process controls and cleaning techniques, problems Kimmel said largely account for the relatively high number of defective mask sets at 130 nm.

Not commercially practical

The early EUV mask blanks developed at Livermore produced a few defect-free mask blanks, proving the feasibility, Kemp said, of the EUV method. But the industry is far from where it needs to be to make EUV lithography commercially practical, he added.

To keep costs manageable, mask substrate makers need to achieve 70 percent yields. To ensure that seven out of 10 mask blanks are free of printable defects, Kemp said, will require an average rate of three defects per 1,000 square centimeters of mask blanks. The current rate of defects per mask blank is 10, Kemp said. Because EUV lithography is aimed at the 45-nm node expected in 2007, defects of 30-nm are considered yield killers.

Since some of the defects come from the deposition tool itself, developers at Albany will try to improve those devices, Kemp said.

Indeed, the mask industry is moving toward next-generation metrology, inspection and cleaning tools that will be critical to the success of the EUV effort. Cryokinetic, or laser-induced, cleaning processes are being compared with new forms of wet cleaning. However, the binding force of such small particles is such that it is difficult to blast them off the surface of the mirrored mask blanks without damaging the reflective coatings, Kemp. said.











  Free Subscription to EE Times
First Name Last Name
Company Name Title
Email address
  Click here for your Free Subscription to EETimes Europe
 
CAREER CENTER
Ready to take that job and shove it?
SEARCH JOBS
SPONSOR

RECENT JOB POSTINGS
CAREER NEWS
Federal CTO Sees IT Leading U.S. Out Of Recession
Aneesh Chopra is looking to other CIOs to advise him on fleshing out a more detailed agenda to best serve the president's IT agenda.

For more great jobs, career related news, features and services, please visit EETimes' Career Center.



All White Papers »   

  Around Silicon Strategies

FPGA startup crunch: These articles are part of a series that examines the status of various FPGA startups in light of the economic recession. Startups Abound Logic, Achronix Semiconductor and Cswitch are all on the hot seat. More...

10 fab technologies on the hot seat: There's trouble brewing in chip-making paradise. Delivery of chips at 32-nm and beyond won't be a cool breeze. EE Times has constructed the following list of 10 fab technologies that could make or break future IC scaling. More...

6 fab technologies on the bubble: It isn't going to be a slam-dunk to deliver chips at 32-nm and beyond. See our story about 10 fab technologies on the hot seat. Then read this article: 6 technologies on the bubble. More...

Our take on Intel-River: With its acquisition of embedded software leader Wind River Systems Inc., Intel Corp. has unambiguously signaled that it is again attempting to diversify beyond X86 processors. Here's our take on the deal. More...

CEVA's reversal: When Gideon Wertheizer, CEVA's CEO, came to New York to ring the closing bell at Nasdaq to celebrate the company's 10th year anniversary, he talked about CEVA's 21.6 percent revenue growth in 2008. More...

Hot technologies to watch for in 2009: Every technologist, marketer, industry analyst and reporter on a hunt for the next big thing is bracing for the 2009 Consumer Electronics Show scheduled less than a month away. More...

Top 20 predictions for semis in 2009: To help sort out the confusion in the market, EE Times has released its own chip forecasts--and other predictions--for 2009. So, what will happen in analog, FPGAs, foundry, memory, MPUs and other sectors? More...

Silicon 60 version 8.0 The EE Times 60 Emerging Startups list, first published in April 2004, has been updated to version 8.0 to reflect the latest corporate, commercial, technology and market conditions. More...

 
Education and
Learning


Learn Now:












Home | About | Editorial Calendar | Feedback | Subscriptions | Newsletter | Media Kit | Contact | Reprints|  RSS|   Digital|  Mobile
Network Websites
International
Network Features




All materials on this site Copyright © 2009 TechInsights, a Division of United Business Media LLC All rights reserved.
Privacy Statement | Terms of Service | About