The company said that it has shipped R&D tools for laser annealing over the past 12 months, that it has taken orders for the first production tools, which it plans to ship at the end of this year, with volume-production shipments expected to commence in 2004.

The laser thermal processing (LTP) capability is the result of nine years of development.

The LTP technology is expected to overcome current thermal diffusion limitations by accelerating anneal and activation times. And like its predecessor, rapid thermal processing (RTP), which enabled the submicron era, Ultratech expects LTP to change the landscape by becoming a key enabler of the nanotechnology era.

LTP is expected to improve both device reliability and yields,leading to manufacturing productivity gains. An alternative approach, flash lamp annealing (FLA), is being proposed by Toshiba (see June 13 story).

Ultratech cooperated with chipmakers in both the United States and Japan to validate the technology, and has laser annealed thousands of 200-mm and 300-mm diameter wafers, the company said. The technology has demonstrated the ability to activate extremely shallow junctions and contacts in nanoseconds, while using zero thermal budget, the company said.

"Our customers and development partners tell us that LTP will be needed for the 65-nm and below technology nodes, and will be especially important to future SoC (System on Chip) and microprocessor devices," said Somit Talwar, Ultratech's vice president of laser technology, in a statement.

Talwar said that laser processing and projection lithography experts had been paired to tackle the challenge

Ultratech test results demonstrate abrupt profile junctions with high surface concentrations down to the 20-nm technology node, the company said. Tests also show that process results are relatively insensitive to device and wafer pattern densities, the company said.

The company's first commercial product based on the new LTP technology platform will be for laser spike annealing (LSA).

The ITRS roadmap requires shallower junction with lower resistance when the logic gate scaling goes narrower. In the 65-nm node, it indicates that the depth of the extension, a shallow extended area from each of the source and the drain to separate them even under a narrow gate, should be in the range of 10-nm to 17-nm, and that the sheet resistance of p-MOSFET is 760 ohms/square in the latest roadmap.