Last week, Intel leaked some details about its "tri-gate" transistor at the Intel Developer Forum (IDF) in San Jose (see Sept. 12 story). But in a briefing at IDF, the company described more details about the technology, claiming it has demonstrated a fully-depleted, CMOS-based "tri-gate" structure, with 60-nm (0.06-micron) gate lengths.

The company's tri-gate transistor is still an R&D project, but the microprocessor giant dropped hints it could deploy this three-dimensional or non-planer technology in chip designs by the second half of this decade.

The possible shift towards tri-gate structures could undermine Intel's other, next-generation transistor project, dubbed the "TeraHertz transistor," according to analysts. Introduced last year, the "TeraHertz transistor' makes use of a conventional or planer structure, which is also geared for the second half of this decade (see Nov. 25, 2001 story).

Analysts indicated that Intel may be moving down the tri-gate path--and for good reasons. Advanced Micro Devices, IBM, Taiwan Semiconductor Manufacturing Co. Ltd., and others are developing competitive devices, based on a double-gate transistor structure, it was noted.

At IDF, Intel outlined the importance of these new transistor structures to enable Moore's Law in the future. Non-planer transistors will enable higher-performance chips that use less power, said Gerald Marcyk, director of components research at Intel Labs, the company's R&D arm.

"The industry will have to make a transition from planer to non-planer transistors," Marcyk said. "The problem with planer transistors is that they draw too much current in the off state and they are too leaky," he said in an interview with SBN at IDF.

A tri-gate transistor with fully-depleted SOI exhibits lower leakage than standard CMOS transistors, according to Intel. And the tri-gate with "spacer-defined fins" has the potential to deliver 20% higher current than today's structures, according to the company.

Not surprisingly, the company also insists the tri-gate structure has several advantages over the rival double-gate transistor. Intel's tri-gate is more "manufacturable" than fully-depleted planar and double-gate structures, according to Marcyk.

And the new transistor technology will not require exotic fab gear; it will make use of existing 300-mm equipment, including lithography tools, he added.

So what happens to the "TeraHertz transistor"? Officials from Intel claimed it will not scrap the "TeraHertz transistor" in favor of the tri-gate structure. The tri-gate structure is simply an "extension" of the "TeraHertz transistor," according to Marcyk.

It's unclear if Intel will put the "TeraHetz transistor" or the tri-gate structure into production. At present, the tri-gate transistor is a "research project," he added.

Details of the new tri-gate technology will be presented at today's International Solid State Device and Materials Conference in Nagoya, Japan.