The results of fabrication experiments show that thin barrier films, key components for advanced copper chip wiring, would meet the electrical and functional demands defined for the end of the International Roadmap for Semiconductors (ITRS), which extends as far as 2016. In addition the work was achieved without requiring novel atomic layer deposition techniques.

The ITRS expects a reduction of the barrier thickness from 12-nanometers at the 100-nm process node in 2003 to 2.5-nm for use with the 22-nm process technology node in 2016.

The Infineon researchers' goal was to investigate the scaling limits of the current Ta/TaN barrier technology and its compatibility with the end-of-roadmap target values. These electrically conducting films separate the copper metal lines from the surrounding dielectrics used for electrical isolation. Hermetic encapsulation of copper lines has proved necessary to prevent the diffusion of copper into the dielectric isolation, and in particular from reaching the transistors below the wiring layers in the chip.

The readiness of copper to diffuse means that without proper containment it can pollute other material systems in the IC and within the transistor copper can prevent device operation.

An ultrathin film provides a very low electrical resistance and means that vias between metallic layers can be kept as short as possible.

Infineon's labs have demonstrated a functioning barrier against copper diffusion with film thicknesses of less than two nanometers, meeting the same reliability requirements as 50-nm thick barrier films in a current semiconductor product, Infineon said.

"With its lower electrical resistance and its higher ruggedness against electro-migration copper shows clear advantages for high performance ICs. But to make this material usable as an interconnect material for future chip generations, great effort has to be spent on preventing any diffusion of copper," said Karl Joachim Ebeling, head of corporate research at Infineon Technologies, in a statement. "The recent results mark a significant milestone to provide all the high sophisticated technologies needed to manufacture the further shrunken next chip generations."

The silicon wafers used for the electrical assessment of the embedded copper lines were processed with standard semiconductor manufacturing equipment and processes developed in Infineons Munich cleanrooms.