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Toshiba proposes flash lamp annealing for 65-nm node
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EE Times


TOKYO -- Flash lamp annealing (FLA) technology will overcome annealing difficulties at the 65-nm manufacturing process technology node, Toshiba Corp. claimed at the Symposium on VLSI Technlogogies being held in Kyoto.

Toshiba has proposed the FLA technology replaces rapid thermal annealing which may struggle to scale down to smaller geometries.

Among various approaches for the next generation annealer including laser annealers that many considered to have the most potential.

"I believe that only our flash lamp annealing system has made wafer level devices of 65 nm node available for evaluation," said Kyoichi Suguro, chief specialist at Toshiba process and manufacturing engineering center of Toshiba.

Three companies, Toshiba, Dainippon Screen MFG Co., Ltd. (www.screen.co.jp) and Ushio Inc. (www.ushio.co.j) teamed up to develop the FLA technology.

Ushio provided Xenon flash lamp technology. Dainippon Screen is in charge of system assembly. Toshiba oversees the total project and is providing requirements from the viewpoint of a device manufacturer. They are going to promote the FLA tool as the de facto standard annealer for the 65-nm node and more advanced devices.

The ITRS roadmap requires shallower junction with lower resistance when the logic gate scaling goes narrower. In the 65-nm node, it indicates that the depth of the extension, a shallow extended area from each of the source and the drain to separate them even under a narrow gate, should be in the range of 10-nm to 17-nm, and that the sheet resistance of p-MOSFET is 760 ohms/square in the latest roadmap.

The target of sheet resistance, which is the resistance of the extension, is achievable with current technology. But there is a trade-off relation between the junction depth and the sheet resistance, it makes more difficult to meet the both requirement.

For example, current rapid thermal annealing (RTA) using halogen lamps can form the extension with low resistance but the depth of the extension becomes large, over 40-nm, according to Toshiba.

Toshiba engineers observed that shallow extensions of about 10-nm, which satisfy the ITRS roadmap target for the 65-nm node, can be formed by the ion implantation process. However, the subsequent RTA process grows the extensions deeper to around 40-nm.

"So we thought that annealing technology should be improved," said Suguro, who has been advocating the necessity of high-speed annealing technology, faster than RTA, for nearly a decade.

Toshiba, Ushio and Dainippon Screen started a joint R&D in 1999 using Xenon flash lamps seeking for new annealing technology better than halogen lamp based annealing.

The Xenon lamp of the flash lamp annealer heats and maintains a wafer over 900 degrees centigrade just for 0.8 milliseconds, about 1/3000 compared to about 2 seconds by presently used RTAs.

Xenon lamp emits light almost in a visible wavelength range. Silicon absorbs a visible light better than infrared light. Halogen lamp's light ranges from visible to mostly infrared range.

The FLA tool uses rapid heating and cooling and efficient absorption of the energy at silicon wafer surface. It does not grow the depth of extensions deeper but maintains almost the same level as the depth immediately after ion implantation process.

The FLA system consists of a flash lamp unit that houses multiple tube-shaped Xenon lamps with reflective plate at the back and a hot plate that pre-heat a wafer to 300-600 degrees centigrade.

All the factors such as lamp layout, shape and characteristics of the reflection plate, and the distance between the lamp and a wafer, were optimized to anneal a wafer uniformly, said Suguro. But the detail of the system structure was not disclosed.

The pre-heating is an important idea to solve ununiformity subject to cause by flash lamp annealing. Depending on patterns on the wafer, the wafer surface is not uniformly heated when only flash lamp annealing is used. By pre-heating the whole wafer on the hot plate, the flash lamp can anneal the wafer surface uniformly with lower energy.

Sugaro said he expects as the result, the FLA tool can simply replace present RTA tools.

The R&D team has already completed a beta tool. The beta tool handles 200-mm diameter wafers, but production tool will be ready for 300-mm wafers. The R&D team intends to complete development of the production tool so that it will be able to work in a line by 2005. Dainippon Screen will market the production tool.






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