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Motorola claims 20% benefit from low-k at 0.18-micron
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Silicon Strategies


AUSTIN, Texas ---- Having targeted its 0.13-micron CMOS manufacturing process technology as the introduction point for low-k interconnect dielectric, Motorola Inc. has successfully transferred the system back to its 0.18-micron silicon-on-insulator process and has been delivering products for over a quarter of a year, the company said today (June 2, 2003).

Motorola has applied the process to PowerPC microprocessor products including the G4 PowerPC processor, Motorola's MPC 7455 and the recently introduced 7457, and chips made using this process run up to 20 percent faster than those made without it and at lower power while maintaining high yields and reliability, the company said.

Company executives would not speak about clock frequencies or power savings specific to the PowerPC designs that are thought to be made for computer company Apple Corp., but gave as an example the boosting of what had been a 1-GHz clock frequency processor to 1.2-GHz clock frequency by the use of low-k.

Within a matter of weeks the company expects to also take the benefit of low-k with copper metal at the 0.13-micron process node. "We'll be in 0.13-micron in the third quarter. Our goal is to stay with a frequency doubling every 18 months or so, and get into the 2-GHz range for PowerPC, but at very low power consumption of say 20 watts," said Dirk Wristers, director of device/integration for Motorola's MOS-13 wafer fab. "The frequency could be higher if we were at higher power."

"Motorola was one of the first semiconductor manufacturers to introduce copper -- that's a big advantage in working with low-k materials," said Wristers. "Many other companies are trying to introduce several new materials at once, which is a huge challenge. We've solved the problems associated with copper interconnects and have been shipping products since 1999. This means we have been able to focus our resources on solving the challenges unique to low-k dielectrics."

Low-k dielectric films have been one researched extensively over the past few years. The lower the k value, the lower the capacitive coupling between neighboring signal lines, and the faster switching that is possible, or the less power is consumed at a given frequency. But because of the complexity of the materials systems and need to use additional materials and prove out their reliability, so far few companies have brought products to market with the technology.

"Indeed some companies are delaying the introduction of low-k to the 90-nanometer node," said Wristers.

Motorola's progress so far is based on the use of so-called Black Diamond carbon-doped oxide film, an approach to low-k developed by Applied Materials Inc. The process utilizes a hydrogenated silicon oxycarbide (SICOH) film.

"We've looked at all of the companies offering low-k technology, spin-on and CVD chemical vapor deposition materials," said Victor Wang, manager of process development at MOS-13. "It's well-known we had a joint-development program with Applied Materials."

However, despite Motorola's successful introduction of low-k at 0.18-micron, soon to be followed at 0.13-micron, the low-k solution going forward to 90-nm manufacturing process technology could see a change.

Wristers pointed out that Motorola has adopted a collaborative approach to future process technology development and that work with Philips and STMicroelectronics at Crolles in France is a key part of that. "We're certainly looking at Trikon in Crolles," Wristers said referring to Trikon Technologies Inc. of Newport, Wales, which offers a low-k materials system it calls Orion.

"At 90-nm we're exploring other solutions with lower k values. Trikon is probably the leading CVD candidate," confirmed Wang.






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