In various papers at ISSCC, Intel plans to describe three new, low-power "building blocks" to enable high-speed processors, including a 5-GHz integer execution core and an integrated 6.5-GHz arithmetic-logic unit (ALU) and scheduler. It will also describe a method to reduce the power consumption in chips by utilizing "forward and reverse body bias" technologies as well.

Intel claims these "building blocks" will enable the development of 5-GHz chips at 0.13-micron process technologies--at room temperature. But the company is aiming these technologies for next-generation processor designs, said Justin Rattner, an Intel Fellow and director of the company's Microprocessor Research Laboratories.

"We would expect to see products based on these technologies at the 90-nm (0.09-micron) node, and most certainly, at 65-nm (0.065-micron)," Rattner said during a presentation for press and analysts in San Francisco last week. The event was intended to preview the company's activities at ISSCC.

At present, Intel is shipping chips, based on its new, 0.13-micron process technology. It is expected to roll out 90-nm chips by 2003 and 65-nm designs in 2005, according to Intel's roadmap.

By the end of this decade, the company is also expected to develop and ship processors that run at speeds from 10-to-20-GHz, according to analysts. But to enable these high-speed chips, Intel is scrambling to address an overlooked, but key issue: power consumption.

In fact, if processors continue to use conventional transistors, then future devices could one day dissipate as much power as a nuclear plant--or even the sun's surface, according to Intel.

In response, Intel has been devising some new and key transistor-level technologies to reduce power consumption. The company is working on what it calls the TeraHertz transistor, which marks the company's initial use of high-k dielectrics, epitaxial wafers, and a real shocker--silicon-on-insulator (SOI) technology. Until recently, Intel dismissed SOI technology for processor designs (see Nov. 25 story ).

At this week's ISSCC event, Intel will put more pieces of the puzzle in place to enable low-power designs. Besides the TeraHertz transistor, Intel is also embracing what it calls "forward and reverse body bias" technology in chip designs.

Some of Intel's intentions were leaked to the media last year. Traditionally, processor suppliers have relied on changing the threshold voltages of a transistor to manipulate performance. Lower-voltage transistors are used in circuits where performance is critical--at the expense of higher leakage current. High-voltage transistors are used where performance can be sacrificed.

Intel hopes to take that a step further by having the body to be either forward- or reverse-biased. That technique could be applied to either the high- or low-voltage transistors (see Nov. 9 story ).

Forward bias enables a 23% reduction in active power in chip designs, while reverse bias cuts stand-by leakage by three-and-a-half times over current technologies, according to Rattner.

Intel is well on its way in bringing this technology to fruition. At ISSCC, Intel plans to describe a CMOS-based, router chip with an integrated body-bias feature. The 10.1- x 10.1-mm device is a 1-GHz, 6.6-million transistor IC, based on 0.15-micron technology.

Intel dropped hints that it would develop processors with on-chip body-bias functions, reportedly called signal generators. This technology "does not require any new manufacturing steps,' Rattner said. "It also doesn't take that much real estate on a processor designs," he told SBN.

The company plans to describe two other "building blocks," including a 6.5-GHz ALU and scheduler. Scalable to 9-GHz, the ALU is a 1.1-volt device that has a power consumption of 120mW.

Perhaps the key "building block" is a 5-GHz integer execution core. Based on 0.13-micron technology, the 1.16- x 1.44-mm device is a dual-voltage, CMOS-based unit, with a power consumption of 267mW.

The integer core itself consists of several key components, including one block that includes a 32-bit executive core, ALU body-bias control circuit, data-control unit, register file, and sleep circuit, according to Intel. Meanwhile, the core also includes a clock chip, FIFOs, and a scan control unit.

The core isn't ready for production-yet. "It's a simple integrated core operating at 5-GHz," Rattner said.