At ISSCC, Intel plans to give six separate papers on McKinley, a 1-GHz, 64-bit processor line for use in high-end servers. The company plans to outline some new features of the processor, including an integrated, Level 3 cache design that promises to boost the overall speeds of the device, according to Intel executives at a press event in San Francisco last week. The event was intended to preview the company's activities at ISSCC, which will be held in San Francisco this week.

Intel itself has been talking about McKinley for the last year and has been sampling the chip since early-2001 (see Aug. 28 story ). The processor is expected to compete against similar 64-bit chips from Advanced Micro Devices, IBM, MIPS, and Sun Microsystems, according to analysts.

McKinley is also the follow-on chip to Intel's current 64-bit processor--dubbed Itanium, which was co-developed by Intel and Hewlett-Packard Co. at a reported cost of $1 billion.

But the Itanium chip was two years late to the market, and so far, has been a disappointment in terms of sales for Intel, according to analysts. Now, system manufacturers are waiting for the new and improved McKinley processor for 64-bit computing applications (see May 25 story ).

But in a move to hedge its bets, Intel is reportedly developing a 32/64-bit microprocessor technology that could appear if the company's current or future 64-bit chip lines should fail to gain market acceptance. The technology is reportedly called "Yamhill" (see Jan 25 story ).

While Itanium and McKinley are full-fledged 64-bit chips, "Yamhill" is a software and hardware technology that will add "64-bit extensions to Intel's x86-based 32-bit architecture, which is similar to what AMD is doing," said analyst Nathan Brookwood of Insight64 of Saratoga, Calif. Brookwood was referring to AMD's own, 64-bit processor line--dubbed Hammer, which is due out in early-2003.

It's unclear if Intel will release "Yamhill" in the market. But if the company should commercialize the technology, it could undermine the adoption and sales of McKinley and future 64-bit chips from Intel, according to Brookwood.

Intel remains mum about "Yamhill," which is reportedly being developed in Hillsboro, Ore. "I cannot confirm or deny codenames," said Pat Gelsinger, chief technology officer of Intel, in a brief interview with SBN at the press event last week.

Officials from Intel spent more time in describing McKinley, a 1-GHz, 221-million transistor device. At present, the current Itanium processor is an 800-MHz chip, which features a 266-MHz, 64-bit bus and 10 pipeline stages, for a total bandwidth of 2.1-gigabytes-per-second. It also has 32-KB and 96-KB of on-die Level 1 and Level 2 cache, respectively, and 48-MB of on-board Level 3 cache.

In comparison, McKinley features a 400-MHz, 128-bit-wide bus and eight pipeline stages, for a total bandwidth of 6.4-gigabytes-per-second. "McKinley will deliver one-and-a-half to two times the performance than Itanium,'' said John Crawford, an Intel Fellow and director of the McKinley architecture, during the presentation.

At ISSCC, Intel also plans to discuss the chip's on-die, 3-MB Level 3 cache. The new Level 3 cache is said to be 85% more efficient but takes up 20% less area than competitive designs, Crawford said. The new design will provide "a huge reduction in latency and system power," he said.

McKinley also has a Level 1 cache with a 1-cycle latency period. It also has a Level 2 cache bandwidth of 64-gigabytes-per-second--or roughly four times the performance of RISC designs, Intel said.

In any event, analysts were impressed with the chip. "It's the Itanium done right," Brookwood concluded. McKinley is currently sampling for what the company calls "pre-production pilot systems." The chip is scheduled to ship in mid-2002.