The new partnership, announced on Thursday (see Jan. 31 story), signals the phase-out of an R&D alliance between AMD and Motorola Inc., which have been jointly developing copper-based CMOS processes for several years. That partnership will officially end after the 100-nm (0.10-micron) technology node, said Hector de J. Ruiz, president and chief operating officer of AMD.

"Motorola and AMD jointly came to the conclusion that the 65-nm effort needs to be very closely tied to the manufacturing effort," explained Ruiz, during a teleconference with analysts and the press on Thursday. "This technology is going to be challenging from many points of view. The intricacy and the linking that must exist in development and manufacturing is more crucial than ever."

For UMC, the new partnership with AMD signals possible changes to its partnership with IBM Corp., which has been teamed with the Taiwan foundry company and Infineon Technologies AG of Germany to create common 0.13- and 0.10-micron processes under the "WorldLogic" alliance (see Jan. 27, 2000, story). The AMD partnership is specifically targeting processes for high-performance microprocessors, making it somewhat different than the copper-based logic technology developed with IBM, said Robert Tsao, chairman and chief executive officer of UMC.

"With this new input from the AMD alliance we may have some review with IBM to make some adjustment," he said while fielding questions during Thursday's conference call.

For more than a year, Motorola and AMD have been rumored to be candidates for a joint-venture 300-mm fab. However, cutbacks in Motorola's own capital spending and wafer-fab plans along with other issues apparently ended discussions on a possible venture. In fact, Motorola is now closing plants and moving to increase its use of outside foundries under an "asset light" strategy (see Jan. 23 story). Meanwhile, AMD was looking for a high-volume production partner to support its intense battle with Intel Corp. for PC processor market share.

AMD and Motorola jointly decided to wind down their cooperative development efforts after the "HiPerMOS 8" (HiP8) 0.10-micron CMOS process generation, said Ruiz, who was president of Motorola's Semiconductor Products Sector prior to joining AMD as president and COO two years ago. Now, AMD plans to shift development from Motorola to "our UMC partner so that we can intersect a manufacturing capacity in 2005," said Ruiz in the conference call.

At present, few details are know about how AMD and UMC will fabricate 0.065-micron processors on 300-mm wafers, except that it will involve common copper interconnect processes and low-k dielectrics, which will be used by both companies in their own plants outside of the Singapore venture later this decade.

AMD and UMC officials said they were not sure yet whether the 0.065-micron technology will employ extreme ultraviolet (EUV) lithography or 157-nm optical tools for exposure of minimum feature sizes.

EUV or 157-nm lithography?

"EUV has a pretty good opportunity there," said Fu Tai Liou, chief officer of sales and marketing at UMC. The company's former chief technology officer also noted that 157-nm lithography development had been delayed in the chip industry as suppliers focused immediate attention on new 193-nm argon-fluoride (ArF) exposure tools and materials for 0.13-micron and below processes. The AMD-UMC partnership is ready to pursue "which ever comes first EUV or 157-nm," he said.

While the ultimate target is to have a common 0.065-micron process for high-performance microprocessors by mid-2005, UMC and AMD both expect to see some jointly-developed modules introduced in prior nodes, such as the 90-nm (0.09-micron) design-rule generation. UMC has developed a baseline process that uses chemical vapor deposition (CVD) for low-k dielectrics in copper dual-damascene processes that is a strong candidate for future technology nodes, according to the officials at the company. UMC has also worked with IBM on spin-on dielectrics, which now appears to be losing out to CVD, according to comments made in the conference call.

UMC officials promised not to be running multiple copper processes in its own foundry fabs and in the AMD joint venture. The main difference between the AMD joint-developed processes and UMC's other foundry technologies will most likely be in front-end-of-line (FEOL) fabrication steps for transistor structures, gates, and other devices used in "microprocessor-performance" ICs. These high-performance ICs could be graphics chips or embedded processors for UMC's foundry customers in addition to AMD's PC microprocessors. The back-end-of-line (BEOL) processes in the 0.065-micron node will be common across all AMD and UMC processes after 2005, according to the plan.

The changes in technology partnerships underscore the difficulties of maintaining joint-development alliances while manufacturing strategies continue to shift because of high capital costs for 300-mm fabs and volatile market conditions.

"At AMD, we believe it is time to revisit the basic business model for the 'independent' device manufacturer IDM that relies on leading-edge technology in the semiconductor industry. Flexibility and timing are still the keys to success but the way to optimize this has fundamentally changed," said Ruiz, referring to the huge costs of building, equipping, and operating 300-mm (12-inch) wafer fabs. The AMD president added that operational flexibility will be crucial to achieving acceptable fab utilization rates and profitability in the 300-mm era. The 300-mm fabs promise "substantially more than 30% cost savings compared to today's 200-mm facilities," he added.

"Our joint venture with UMC will enable AMD to make the transition to 300-mm manufacturing at precisely the right time," Ruiz told analysts and the press. "We will gain immediate access to an existing 300-mm wafer fab for research and development activities at UMC and in the next few years we expect require substantial additional production capacity.

"We believe the optimal time for us to make the transition to high-volume production on 300-mm wafers is in the mid-2005 timeframe when we expect to begin starting production on the 65-nm node," he added.

Battling the giant

AMD also believes its approach will help it compete against Intel's huge capital spending budget, which has been more than seven times the amount spent by AMD in recent years. In fact, AMD is increasing its capital spending 20% to $850 million in 2002, while Intel's 24% decrease this year still gives it the edge at $5.5 billion, following a record $7.3 billion in 2001. The majority of Intel's fab equipment spending will be for 300-mm tools in 2002.

But AMD is fighting back with its foundry new strategy. "In order to get the cost benefits of going to 300-mm wafers you need to utilize the factory," said W.J. (Jerry) Sanders, chairman and CEO of AMD. "Individually, we would not be able to fill up a factory as quickly as we would want and the cost burden could be significant. This way we will get a much higher utilization and that is going to drive our cost down.

"Our competitor Intel is going to have to ramp production in the meantime and absorb the full capacity costs of 300-mm fabs," Sanders told analysts and the press. "We think we have a flexible advantage, which will enable AMD to meet its volume requirements and enable UMC to make more money by having greater utilization of the factory at any given time."

As for AMD's partnership with Motorola, the door is still open for future collaboration, according to Ruiz. He said the past joint-development efforts have been highly successful in enabling AMD's Fab 30 in Dresden to ramp copper processors into volume high yields.

"This is an evolution of partnerships and alliances," he noted. "We expect as we go forward that in some form we will continue working with Motorola on very specific modules ... but as far as the high-performance, leading-edge processor technology, we are now going to shift towards a joint effort with UMC with a purpose of making it very, very closely aligned with the manufacturing activities."