The proposed DDR-II standard has been in the works for months and is supposed to replace existing DDR SDRAMs, which is now being called "DDR-I." The "mainstream DRAM" market is also expected to migrate from the 200/266-MHz versions of DDR SDRAMs in the market today to the 333/400-MHz products and then to DDR-II, said some memory makers at the JEDEX conference.

Not everyone agrees, however. Some suppliers believe there is no real market for the 400-MHz version of DDR, dubbed DDR-400. Instead, the "mainstream memory" market will jump directly from the DDR-333 products to the new DDR-II spec, according to some industry leaders at the conference on Monday (see March 25 story).

But all memory makers are scrambling to develop DDR-II DRAMs, with plans to sample parts by late 2002 or early 2003. The DDR-II market is expected to move into the mainstream by 2004, said Katsuyuki Sato, deputy general manager of the technical marketing division for Japan's Elpida Memory Inc. The Tokyo-based company is a joint DRAM venture between Hitachi Ltd. and NEC Corp.

This month, JEDEC will finalize the DDR-II specification. A support chip definition for the technology is due out in June of this year, while a module specification is slated for September.

According to the roadmap from the JEDEC organization, DDR-II memories for the PC and other markets will eventually come in 400-, 533-, and 667-MHz speed grades, Sato said during a presentation at the JEDEX conference. JEDEX is sponsored by the JEDEC Solid State Technology Association. (JEDEC was once known as the Joint Electron Device Engineering Council.)

For the high-speed graphics market, DDR-II memories will be offered in two speed grades: 800- and 1,000-MHz, Sato said. DDR-II memories will come in 200-, 220- and 240-pin FBGA packages, he said.

Initially, DDR-II memories will be 1.8-volt parts that will come in 512-megabit densities, according to the Elpida executive. "We are fabricating DDR-II memories now," he said, noting that the products will be based on 0.13-micron process technology.

DDR-II will have the same commands as DDR-I memories, but the new technology will feature 4 and 8 burst lengths, CAS latency with no half-cycle latency, and no interrupt commands. It will also include write latency and read latency-1 specifications.

New features for DDR-II include posted CAS, differential strobe, off-chip output driver calibration (OCD), on-die termination (ODT), and burst interrupt. It will also include an SSTL 1.8-volt I/O interface and 1-kilobyte addressing for 512-Mbit-by-4 or by-8-bit memories and 2-Kbyte for 512-Mbit-by-16-bit configurations.

DDR-II will also feature a pre-fetch size of 4 bits; in comparison, DDR-1 technology has a pre-fetch size of 2 bits.