The 52-megabit SRAM test chips are being used as Intel's prototyping vehicle for the new 90-nm (0.09-micron) process technology, which is called P1262. The process is now scheduled to be placed into volume production in 2003, beginning with the recently disclosed "Prescott" Pentium 4 processor.

Intel's 90-nm seven-layer copper-metal technology is being readied exclusively for use in 300-mm wafer fabs. The process uses 193-nm wavelength lithography for the minimum feature sizes and 248-nm scanners for less critical dimension layers.

"We expect that the transistor gate-length dimension will scale to less than 50 nm 0.05 micron on the 90-nm technology that will be introduced next year for production of products," said Mark Bohr, an Intel fellow and director of the company's process architecture and integration unit in Santa Clara, Calif. Other chip makers have announced smaller gate-lengths targets for the same technology--such as a 37-nm feature size in a 90-nm process disclosed by Texas Instruments Inc. last month (see Feb. 4 story).

But more importantly, the 1-micron² cell size "is the smallest reported in the industry to date," Bohr said. "Intel is the first to achieve this milestone. The SRAMs have a capacity of 52 megabits, and this as well is the highest capacity reported by the industry to date," said Bohr in a briefing for technical journalists.

Information about the 90-nm CMOS process has been dribbling out from Intel for several months; however, today's announcement is considered a significant milestone in moving the next-generation technology to production. Intel and other chip makers use SRAMs as test and prototyping vehicles for processes and transistor designs that are eventually used on microprocessors. The Intel SRAM is not a product, but the company plans to use the tiny six-transistor cell in cache memory blocks on its next-generation processors, Bohr said.

Intel continues to keep much of the details secret about the 90-nm process, including the fabrication techniques used to produce minimum transistor gate lengths below 50 nm. Bohr said Intel used a combination of 193-nm photolithography and "very advanced etching" techniques, but he declined to provide any additional details about photomasks or other possible technologies that are most likely needed to make device feature sizes below 50 nm (0.05 micron) with 193-nm wavelength exposure tools.

The new 90-nm process is the first for Intel to use 193-nm step-and-scan tools. Bohr refused to discuss which lithography supplier was providing 193-nm scanners for development or prototyping in Intel's D1C development and early production 300-mm fab in Hillsboro, Ore. The D1C fab became Intel's first 300-mm production line to produce products on 12-inch wafers using 0.13-micron technology (see Feb. 25 story).

"That fab will be converted wholly to 90-nm manufacturing by the end of next year," Bohr said while fielding questions. Intel also plans to transfer the 90-nm process technology to other 300-mm manufacturing fabs, "the first of which is in New Mexico," he said, referring to Intel's complex in Albuquerque.

The 90-nm process increases the number of copper metal interconnect layers to seven from six in Intel's current 130-nm (0.13-micron) Px60 technology, which was placed into production in 2001. The minimum transistor gate length has been shrunk from below 70 nm to below 50 nm in the new P1262 technology, according to Bohr. Intel's follow-on process generation--the planned 65-nm (0.065-micron) P1264 process--will push transistor gate lengths down to below 35 nm and is slated for production in 2005, according to a technology roadmap disclosed by Bohr.

"Why is this announcement of the 90-nm SRAM chip important? It shows that Intel is on track to delivering a new process technology every two years," Bohr said. He also added that it shows Intel is on track to hit its goal of producing a microprocessor with 1 billion transistors by 2007. The SRAM prototype chip has 330 million transistors on a die measuring 10.8 mm by 10.1 mm, he said. In comparison, Intel's "McKinley" version of its Itanium processor has 220 million transistors. Bohr would not say how many transistors would be used on the Prescott processor, which is the first product planned for the 90-nm process technology.

The entire 90-nm fabricated 300-mm wafer--loaded with 52-Mbit SRAMs and other test chips--has 120 billion transistors, Bohr said. Bohr said the 52-Mbit memory was the highest density SRAM ever fabricated. "This is not a paper announcement, and the silicon is real and fully functional," he told a small group of journalists. He would not give out information on the performance of the SRAM.

"These static RAM chips demonstrate all of the 90-nm process features required for microprocessors, including transistors and interconnects," Bohr said. Again, he declined to discuss details about dielectrics or other process-specific features. "Let's save something for later," he added, indicating that more details will be released when Intel is closer to ramping production with the 90-nm technology.

Intel appears to be in near lockstep with other major manufacturers preparing to ramp their 90-nm (0.09-micron) process technologies. TI, IBM, Motorola, and others have disclosed various milestones in recent months in their preparation of launching their technologies by the end of 2003. Bohr would not say exactly when Intel planned to be using its 90-nm process to produce products in 2003, but he suggested that lower volumes of wafers could be running in the Hillsboro D1C fab by the end of 2002.

That schedule and the announcement of the first functional prototype SRAMs is roughly similar to that disclosed by Taiwan Semiconductor Manufacturing Co. Ltd., which has partnered with Royal Philips Electronics N.V. and STMicroelectronics to move 90-nm processes into production in the next year. TSMC--the world's largest pure-play silicon foundry company--said it had successfully produced SRAM test chips with 1-Mbit and 4-Mbit densities using the 90-nm technology, and the Taiwan chip maker plans to begin pilot production with the process in the fourth quarter of 2002 (see March 5 story).

TSMC's SRAM cell size was larger than Intel's reported prototypes at 1.36 micron². The Taiwan foundry company and its partners said they plan to further reduce its cell size to 1.27 micron² by the end of the year.

--J. Robert Lineback reporting in the U.S.