TSMC, Philips, and STMicroelectronics said test devices for the 90-nm process have been successfully fabricated by all three partners. Philips and ST teamed up to fabricate the test chips in a joint-development pilot line in Crolles, France, while TSMC produced its devices in an R&D fab line in Hsinchu. Prototyping of products is expected to start in the second half of 2002, said the three companies.

For TSMC--the world's largest silicon foundry supplier--the 90-nm test chips are a milestone that puts the company more than a year ahead of the 2001 International Technology Roadmap for Semiconductors (ITRS), said managers in Taiwan. TSMC said it expects to enter pilot production of its 90-nm process by the fourth quarter of 2002. Volume production of the 90-nm CMOS process will commence almost entirely on 300-mm (12-inch) wafers, according to the foundry company.

"Since we introduced our 0.13-micron process in 2000, TSMC has surged ahead of the ITRS roadmap for new process development," said F.C. Tseng, deputy CEO at TSMC. "With this achievement, we maintain our position ahead of that roadmap."

The 90-nm technology developed by the three partners was validated on fully functional test chips produced on the ST/Philips pilot line in Crolles and at TSMC's Fab 3 R&D facilities during the fourth quarter of 2001, said the companies. The 90-nm process features both dual-damascene copper and low-k dielectrics interconnect structures.

These test chips included 1 megabits and 4 Mbits of embedded SRAM functions. The SRAM density of 735-kilobits-per-mm² is one of the highest in the industry, according to the three companies. The partners said they intend to further increase the density by year's end, reducing the SRAM cell size from its initial 1.36 micron² area to 1.27 micron².

The process development partnership does not currently include an agreement on a joint venture in 300-mm wafer fabrication, as was rumored two weeks ago (see Feb. 21 story). However, much of the future development activity in the three-way process R&D partnership will be conducted on 300-mm wafer systems, leaving the door ajar for future activities that could include volume production.

"The development of this process will give our customers early access to an advanced system-on-chip process that supports high performance processors and peripherals, together with embedded DRAM and SRAM," said Theo Claasen, Chief Technology Officer at Philips Semiconductors in the Netherlands. He added that Philips intends to use the new process technology to "exploit the scalability of our Nexperia architectures to even greater complexities within the shortest time to market." Nexperia is a dual processor architecture for entertainment applications.

The joint project extends existing alliances among the three companies. ST and Philips Semiconductor have been cooperating in joint development of CMOS digital and mixed-signal processes since 1992. ST has been cooperating with Philips in 300-mm development and pilot production at the company's plant site in Crolles(see April 13, 2000, story).

Meanwhile, Philips and TSMC have collaborated in process research and development since the founding of the Taiwan foundry company in 1987. Philips is TSMC's largest shareholder, with about 30% of the company's stock. TSMC and Philips have also formed a $1.2 billion 200-mm wafer foundry venture in Singapore, called Systems on Silicon Manufacturing Co. (see Sept. 29, 1998, story).

"This joint development project is not simply an alignment of design rules," said Joel Monnier, corporate vice president and director of central R&D at STMicroelectronics. "Thanks to our initial collaboration on fundamental technical issues and the ongoing interchange of data, we can be sure that the processes of all three partners in this and subsequent generations will be fully compatible."