Intel's new 1.8-volt "Wireless Flash" memories are being offered in 32-, 64-, and 128-megabit densities. The new flash series is up to four times faster than existing products on the market, according to the Santa Clara, Calif.-based chip giant.

At the same time, Intel also claims to be the world's first company to produce folded and stacked CSP packages for its flash-memory and other chip lines. Intel and Tessera Inc. last year introduced a "folded" stacked-chip packaging technology as a radical new way to place ICs on top each for space savings and lower costs (see May 25 story). Flash chips in both the stacked and folded packages will be available in sample quantities later this year, said Intel.

The company rolled out the new flash-memory and IC packages at the Japanese version of IDF--and for good reason. A key targeted market for these products is 3G cellular phones, especially those being sold in Japan, said Mike Williams, director of marketing for Intel's Flash Products Group.

At present, Williams said, the current crop of 3G cellular phones in Japan are based on 3-volt flash memory devices, which limits the overall talks times and battery life for these products. "The problem is that 3G phones in Japan can't make it through the day," he said, referring to the drain on batteries.

By moving to Intel's 1.8-volt parts, system manufacturers from Japan and other nations can reduce the power consumption in these 3G phones by 40% to60%, thereby boosting talk times, he said, during a U.S. press briefing prior to today's launch. This increased performance results in higher data throughputs for high-end, Internet-enabled cell phones as well, he added.

The 1.8-Volt flash memory line, designated W18/W30, supports burst modes up to 66-MHz with 11-ns subsequent access times, according to Intel. The flash-memory line also combines several major innovations into one product: flexible partition read-while-write operations; synchronous burst and asynchronous page mode read operations; and enhanced factory programming.

The technology integrates flexible partition read-while-write architecture with synchronous burst and asynchronous page mode read operations. In addition, it supports Intel's Flash Data Integrator software version 4, which enables management of code, data and files in flash memory.

In 10,000-unit quantities, the 64-Mbit chip is $14.91, and the 32-Mbit part is $8.97. The 64-Mbit version is sampling and will be in production in July, while the 32-Mbit part will sample in June and be in production in September. A 128-Mbit chip will also be released later this year.

The chips come in 0.75-mm pitch CSP (7x8 ball matrix) and 0.8-mm pitch Stacked-CSP (8x10 ball matrix) packages.

At the IDF Japan event, Intel also announced several packaging technologies. These include stacking multiple, high-density memory and chips in a single CSP package. It also announced a stacked, folded packages that accommodate higher levels of multi-die integration and memory density in a smaller space.

The packaging techniques are crucial in a small form factor device like a cellular phone, where higher levels of memory are required but board space is at a minimum.

--Mark LaPedus reporting from Silicon Valley in U.S.